SU1649535A1 - Fibonacci decimal code adder - Google Patents

Abstract

The invention relates to computing and can be used in specialized machines. 5tA5i35t25t1 The purpose of the invention is to expand the functional features by implementing the operation of subtracting Fibonacci-decimal codes. The device contains, in the first to fourth prohibition elements 17.1-17.4, first and fourth elements AND 18.1-1 o.4, the forward code converter 19 to the additional code, the first to third convolution nodes 20.1-20.3, first through fourth one-bit binary adders 2201-22.4, first through fifth elements OR 23.1-23.5, correction unit 24 and transfer generation node 25 with corresponding links. The summation or subtraction of n-bit Fibonacci-decimal operands is performed in two cycles without the spread of hyphens between decimal places. 3 hp ff, 6 ill., 3 ta bl. 6i4 6i3 6i2 Bi17 with $ (L

Description

13 L

1UL

& 25

-36

23

Utf Mr

AL

f. 201 .1

w

 w ,, З. i-. -. l., - X- f.

"3f73 | 77 | / 7 1 1Шф} 1В2 1в 1 3529l 28 j 27 j 261

202

Ji

nineteen

33

32

J /

thirty

OE 4b CO SL

with en

Jd Idi2 Bi3 8i4

Fig 2

The invention relates to computing and can be used in specialized computers.

The purpose of the invention is to expand the functionality by implementing the operation of subtracting Fibonacci-decimal codes.

FIG. 1 shows a block diagram of a device for summing Fibonacci-decimal codes (three times a day)} in FIG. 2 is a block diagram of a device bit; FIG. 3 is a functional diagram of a character processing node; 4 - functional diagram of the converter of the direct code into the additional code of the discharge, except the younger one, of the device; in fig. 5 is a functional diagram of the direct code converter to the additional code of the lower bit of the device; FIG. 6 is a functional diagram of the transfer generation unit.

The device contains bits 1-3

device, node 4 processing marks, input groups 5.1-5.3 bits of the first addend device, input groups 6.1-6.3 bits of the second term device, input 7 specifying the type of device operation, output groups 8.1-8.3 bits of the device amount, output 9 device signs, output 10 of the device positive overflow signal, the first 11 and second 12 inputs of the transfer of the character processing node 4, the first 13.1–13.3 and the second 14.1–14.3 outputs of the formation of translations of bits 1–3 of the device, the first 15.1–15.3 and the second 16.1-16.3 inputs of setting the mode of bit correction nodes 1- 3 devices.

Bit 1 (2,3) of the device contains the first to fourth prohibition elements 17.1-17.4, the first to the fourth elements AND 18.1-18.4, the forward code converter 19 to the additional code, the first to the third convolution nodes 20.1-20.3, the output 21 of the node 20.3 convolution convolution, first through fourth one-bit binary adders 22.1-22.4, first through fifth elements OR 23.1-23.5, correction node 24, hyphenation unit 25, first through fourth inputs 26-29, and first through sixth outputs 30-35 of the forward code converter 19 to the additional code; sixth, 36, fifth 37, second 38, first 39, fourth 40 and third 41

five

0 5 0

five

30 15 40

45 5o

the inputs of the transfer formation unit 25, respectively, the outputs 42 and 43 of the transfers of the first 20.1 and the second 20.2 convolution nodes.

Node 4 processing signs form the first 44 and the second 45 elements of the ban.

Converter 19 direct code in the additional code of the bit, except the youngest, the device contains from the first to the third elements 46-48 prohibition, the first element And 49, from the fourth to the sixth elements 50-52 ban, the second element And 53, the seventh 54 and eighth 55 prohibition elements, the third element And 56, from first to fifth elements OR 57-61.

Converter 19 direct code to an additional low-order code of the device consists of the first element And 62, the first 63 and second 64 prohibition elements, the second element And 65, the third 66 and fourth 67 prohibition elements, the third element And 60, from the fifth to the eighth elements 69-72 of the ban and the first 73 and second 74 elements OR.

The first hyphenation unit 25 contains AND 75-80 and first 81 and second 82 OR elements, the input 36 of node 25 is connected to the first inputs of the first element OR 81 and the first element AND 75, and the input 37 to the second inputs of the first element OR 81 and the first element AND 75 and the first inputs of the elements AND 76-78, input 38 with the third input of the first element OR 81 and the first inputs of the elements AND 79 and 80, input 39 with the fourth input of the first element OR 81 and the second inputs of the AND elements 76 and 79, input 40 - with the fifth input of the element OR 81 and the second input of the element AND 77, one 41 - with the sixth input of the element OR 81 and the second inputs of And 78 and 82, the outputs of the And 75, 76, 78, 79, 80 elements are connected respectively to the first, second, third, fourth, fifth and sixth inputs of the second element OR 82, the output of which is connected to the output 14 of the node 25, the output of the first element OR 81 is connected to the output 13 of the node 25 "

The device uses decimal bit weights 5, 3, 2, 1. The addition operation takes two ticks. On the first cycle, the sum and transfers of decimal places are formed, and

five.

the second cycle is the cancellation of transfers by simply adding them to the values of the corresponding sums of bits. In this case, there is a rejection of the normalized form of representation of decimal numbers and a decimal place of 10 or 11 is allowed. The addition algorithm is completely identical to the addition algorithm implemented in the prototype,

The operation of subtracting from operand A of operand B can be carried to addition by converting the code of operand B into an additional code, like a code of a negative number. If the operand B code has n decimal bits (from the 0th to (n − 1) -th, then the nth decimal bit is treated as signed.

Positive numbers are represented by:

AI

0 10P + B 0-10 + MP1,

. UO

where В «0.11 is the value of the 1st decimal digit of the number B.

The complementary code of the number is the complement of the modulus of a negative number up to a certain limit value exceeding the maximum possible modulus. At the same time, it is necessary to take into account the need to place negative numbers on the positive portion of the numerical axis in order to ensure the possibility of performing calculations on the adder.

The maximum possible modulus is

/AT/ . ten

+ 2-ZV

+ 10

Therefore, the boundary number may be the number 2 10, but it is possible that negative numbers in the additional code may fall into the region of positive numbers. In order to avoid this, a value equal to 3 FER is taken for the boundary number.

The negative numbers in the additional code are represented as:

mi

3-Y - In IOP + (2-10, -2X - Yu1)

those. the sign bit of the number is preassigned to 1, and the additional code of the significant part of the number is obtained by adding up to 2–10, that is, the additional code of the 1st decimal digit of the negative number is obtained as follows;

Eop pr d- 20 - d- at 1 0;

df °; 18 - + at i 1,2 .... where d. - value of the 1st decimal

t bit direct code number; oap d- - the value of the 1st decimal

extra size

"

-

0

five

0

five

number code; P. Transfer from (i-1) -ro bit.

After the additional code of the number is reduced to a normalized form, the value in the sign bit is 2. After the operand B is transformed, the codes are then added in the manner described above.

The character processing node 4 is intended to allow the formation of the sign of the result and the positive overflow signal, depending on the operation performed in the device and the values of the transfer signals from the device's highest decimal place. It implements

following logic functions: cr P,

WITH

- R.-O) ZI G 1 sh 1

ppf co-pf,

where C-JH is the sign of the result;

Pp - positive overflow signal;

CO 0 - if the addition of operands is performed;

 - if operands are subtracted;

PCT

M

per ge

- respectively, the values of the first and second carries from the highest decade to sign bits.

Converter 19 implements the functions FOR any 1st decimal 0 bit, except the youngest, and the function

f-f ri G6

for the lowest decimal place. Functions - values, respectively, from the first to the fourth binary bits of the additional code

5 corresponding decimal place, f. - f - the same, for the lower decimal place, functions., Ј4 fg- - transfer to the higher bit (occur when the additional code is normalized

0, respectively, of the 1st, lower decimal places). These functions are given in Table. one.

The nodes 20.1–20.3 convolutions are intended to normalize the decimal bit of the operand if its value is greater than 9, i.e. 10 or 11.

Fibonacci-decimal adder is a collection of

71

three one-bit adders 22.1-22.4, designed to sum two Fibonacci-decimal digits of operands A and B, respectively, with weights of 5, 3, 2, 1, interconnected by chains of hyphens based on the summation rules described in the Fibonacti summing device decimal codes.

Correction unit 24 is intended to correct the amount that has passed the normalization at convolution node 20.3, taking into account

transfers P ,, and P from the previous decimal bit of the device. The correction node can be implemented combinational or based on ROM, which is more economical.

ROM firmware card is shown in Table. 2

The transfer generation unit 25 is designed to form the P and PЈ transfers into the subsequent device discharge, depending on the transfers arriving at its inputs from the converter 19, the convolution nodes 20.1-20.3, and the adder 22.4. This is a combinational node that implements the functions P and P, which are defined by the following logical expressions:

l, / h / - AR, T. + „+ P, + + Pr + 7,

one

P “2 P (

 L,

  :

L, / -L.

Pr +, P, R.

Р Р 1 zgb

city H

RL

 R

+ Р „Р,

GGG6

Where

L.

R"

R; p перенос transfer from converter 19 to low-order device;

transfer from converter 19 of the corresponding bit of the device,

transfer from the second node 20.2 convolution;

transfer from the first node 20.1 convolution;

transfer from the fourth one-bit adder 22.4; transfer from the third node 20. 3., convolutions.

Despite the fact that six transfer signals from various nodes of the corresponding bit are involved in the formation of transfer in the subsequent discharge, the maximum transfer value to the next discharge is 2G. One of the six possible transfers allows only one more transfer, excluding completely the emergence of four other hyphenation.

R

LR,

In tab. 3 shows which of the ne

0

five

five

0

five

0

Renos can occur simultaneously.

The device works as follows.

At the same time, the decimal codes of the processed decimal numbers A and B are received at the inputs 5 and 6 of the device. The device 7 receives a zero signal if the numbers A and B need to be added, and a single signal if the number B is subtracted from number A

When adding the input decimal numbers A and B, if any decimal bit of any of the numbers A and B is 10 or 11, then the nodes 20.1 and 20.2 of the convolution of the corresponding decimal bits normalize, resulting in outputs 20.1 and 20.2 convolution nodes, single transfer signals arrive at the corresponding inputs of node 25. If the same decimal bits of both numbers normalize, then a single signal from the transfer output of adder 22.4 and convolution node 20.3 of the corresponding Q digit is excluded. Then, the normalized operand A is fed to the corresponding inputs of one-bit adders 22, and the normalized operand B through the elements OR 23 goes to the corresponding inputs of one-bit adders 22, where the first step of the addition occurs. If, as a result of the summation on the adder 22.4, a transfer to the higher decimal bit occurs, then a single signal is fed to the corresponding input of the node 25. In this case, the sum obtained does not need further normalization. The resulting amount from the outputs of adders 22 is fed to the corresponding inputs of the convolution node 20.3, where, if necessary, the result is normalized, resulting in a single transfer signal through the output of the convolution node 20.3 to the corresponding input of the node 25. Then the result goes to the correction node 24, where correction of the result obtained taking into account the carry from the lower bit,

5 formed by the node 25 junior bit.

When subtracting from the decimal operand A the decimal operand B each

The decimal bit of the latter is fed to the inputs of the converter 19 of the corresponding decimal place, where the source code of the operand B is converted into an additional code. The occurrence of single carry signals to the high order from the outputs of the converter 19 is fed to the corresponding inputs of node 25. The additional operand code B to the OR OR 23 elements is fed to the corresponding inputs of single-bit adders 22. Operand L arrives at the convolution node 20.1, in which happens

its normalization, and to the corresponding inputs of one-bit totalizers 22 Next, in the same way as when adding operands A and B.

Claims (4)

1. A device for summing Fibonacci-decimal codes, containing in each bit from the first to the third convolution nodes, from the first to the fourth one-bit binary adders, the first OR element, the correction node and the formation unit of hyphens, and the first inputs of groups of bits of the first The addend device is connected to the inputs of the first addendum of the first one-bit binary adders of the corresponding device bits, the second to the fourth inputs of the groups of bits of the first term device are connected respectively to the first, The first and third inputs of the first convolution nodes of the corresponding bits of the device, the first and third outputs of the result of the first convolution node of each bit of the device are connected to the inputs of the first terms of the second, third and fourth one-bit binary adders of the same bit of the device, output transfer k- go (k 1-3) of a one-bit binary adder of each bit of the device is connected to the transfer input (kH) -ro of a one-bit binary adder of the same bit of the device; transfer outputs of the second and third o bottom binary accumulators of each bit of the device are connected respectively to the first and second inputs of the first element OR of the same bit of the device, the output of the first element OR of each bit of the device five 0 5 n 0 5 five connected to the transfer input of the first one-bit binary adder of the same bit of the device, the outputs of the second to fourth one-bit binary adders of each bit of the device are connected respectively to the inputs of the first to the third third convolution node of the same bit of the device, the output of the sum of the first the one-bit binary adder and the first to third outputs of the result of the third convolution node of each device device are connected respectively to the information inputs of the first to fourth correction nodes The same device bits, the outputs of the device bits correction units are the output groups of the corresponding device amount bits, the transfer outputs from the first to the third convolution nodes, and the transfer output of the fourth one-bit binary adder of each device bit are connected respectively to the first to third inputs the fourth node of the formation of transfers of the same bit of the device, the first and second outputs of the node of the formation of transfers of the previous bit of the device are connected respectively to the first and second inputs of the the mode of the node subsequent bit correction correction device, that is, in order to expand the functionality by implementing the Fibonacci-decimal codes subtraction operation, it contains the character processing node and in each bit of the device the first to fourth elements are additionally entered And, from the first to the fourth elements of the prohibition, the converter of the direct code into the additional code and from the second to the fifth elements OR, the mth (m 1-4) inputs of the groups of bits of the second term of the device are connected to the first inputs And the x-elements And with the information inputs of the prohibition elements of the corresponding device bits, the input of the operation type of which is connected to the second inputs from the first to the fourth elements And, to the control inputs from the first to the fourth elements of the prohibition of each bit of the device and the input of the setting of the processing node mode into characters, the outputs from the first to the fourth elements AND of each bit of the device are connected respectively to the first GB through the fourth inputs of the direct code converter to the additional code of the same bit of the device, the first to the fourth outputs of the direct code converter to the additional code of each bit of the device are connected to the first inputs of the second to the fifth elements OR of the same bit, respectively the device, the fifth output of the direct code to additional converter is connected to the corresponding input of the transfer unit of the same bit of the device, the sixth output of the direct code converter to the additional code is m The next bit of the device is connected to the corresponding input of the node forming the transfers of the same bit of the device, the output of the first prohibition element of each bit of the device is connected to the second input of the second element OR of the same bit of the device, the outputs of the second to fourth elements of the prohibition of each bit of the device are connected respectively, the first to the third inputs of the second convolution node of the same bit of the device, the first to the third outputs of the second convolution node of each bit of the device are connected to the second inputs from the third to the fifth elements OR of the same device bit, outputs from the second to the fifth elements OR The first and second outputs of the device for distorting the high bit of the device are connected to the first and second inputs of the transfer of the character processing node, the first output of which is connected to the output of the character the device, the second output of the character processing unit is connected to the output of the device overflow signal. 2. The device according to claim 1, of tl and 10 15 20 25 thirty the input of the first prohibition element and the information input of the second prohibition element, the output of which is the second output of the processing unit, the sign of the second transfer input and the first output of which are connected respectively to the second control input and output of the first prohibition element. 3. The device according to claim 1, characterized in that the converter of the direct code into the additional code of the discharge, except the younger one, contains from the first to the eighth prohibition elements, the first, second and third elements AND, from the first to the fifth elements OR, the first input converter direct code to the additional code is connected to the first equalizing inputs of the first, fifth and seventh prohibition elements, the control input of the sixth element, the first information input to the third prohibition element, information input of the fourth element ban and lane the inputs of the first and third And elements, the second input of the direct code conversion body into the additional code is connected to the second control input of the first prohibition element, the control input of the second prohibition element, information inputs of the third and fifth prohibition elements, the first information input of the sixth prohibition element, the second input each bit of the device connect the first element AND and the first input 40 45 50 The second element And, the third input of the direct code generator to the additional code is connected to the second information inputs of the second and six prohibition elements, the control inputs of the third and fourth prohibition elements, the second control input of the fifth prohibition element, the second inputs of the second and the third AND element, the first control input of the eighth prohibition element, and the first inverse input of the first OR element, the fourth input of the direct code to additional code converter is connected to the second control inputs of the seventh and of the seventh prohibition element, the third input of the third element AND and the second inverse input of the first element OR, the third input of which is connected with the output of the first prohibition element, the output of the second prohibition element is connected to the first inputs of the second and fourth elements Since the character processing node contains the first and second prohibition elements, the mode setting input of the character processing node is connected to the information input of the first prohibition element and the control input of the second prohibition element, the first transfer input of the character processing node is connected to the first control five 0 five 0 the input of the first prohibition element and the information input of the second prohibition element, the output of which is the second output of the character processing section, the second transfer input and the first output of which are connected respectively to the second control input and the output of the first prohibition element. 3. A device according to claim 1, characterized in that the direct code converter into the additional code of the bit, except the minor one, comprises from the first to the eighth prohibition elements, the first, second and third elements AND, from the first to the fifth elements OR, the first input of the direct code to additional code converter is connected to the first control inputs of the first, fifth and seventh prohibition elements, the control input of the sixth prohibition element, the first information input of the second prohibition element, the information input of the fourth ele Enta ban, and the first inputs of the first and third And elements, the second input of the direct code to additional code converter is connected to the second control input of the first prohibition element, the control input of the second prohibition element, information inputs of the third and fifth prohibition elements, the first information input of the sixth prohibition element, the second input 5 of the first element And the first entrance 0 five 0 five The second element And, the third input of the direct code converter to the additional code is connected to the second information inputs of the second and sixth prohibition elements, the control inputs of the third and fourth prohibition elements, the second control input of the fifth prohibition element, the second inputs of the second and third elements And the first control input of the eighth prohibition element, and the first inverse input of the first element OR, the fourth input of the direct code to additional code converter is connected to the second control inputs seven th and eighth prohibition elements, the third input of the third element AND and the second inverse input of the first element OR, the third input of which is connected to the output of the first prohibition element, the output of the second prohibition element is connected to the first inputs of the second and fourth elements OR, the output of the third prohibition element is connected to the second the input of the second element OR, the outputs of the first element And the fourth element of the ban are connected respectively to the inputs of the third element OR, the outputs of the fifth and sixth elements of the ban are connected respectively the second and third inputs of the fourth OR element, the outputs of the second element AND, the seventh and eighth prohibition elements and the third element AND are connected respectively to the inputs of the fifth OR element, the outputs from the first to the fifth OR elements are, respectively, the fifth, first, second, the third and fourth outputs of the direct code to additional code converter. 4. The device according to claim 1, of which is inclusive. The fact that the direct code converter to the additional low-order code of the device contains from the first to the eighth prohibition elements, from the first to the third elements AND, the first and second elements OR, and the first input of the direct code to additional code converter is connected to the first inputs the first to third elements of AND, with the first control inputs of the first, second, and eighth prohibition elements and the information inputs of the third and fifth prohibition elements, and is the first output of the direct code to additional converter th code, the second input of which is connected to the second inputs 0 five 0 five 0 five the first, second and third elements And, with the second control inputs of the first, second and eighth prohibition elements and information inputs of the fourth and sixth elements of the prohibition, the third input of the direct code to additional code converter is connected to the third input of the first element And, the third control inputs first and eighth prohibition elements, information inputs of the second and seventh prohibition elements, and control inputs of the third and fourth prohibition elements, the fourth input of the direct code converter in the additional The user code is connected to the fourth input of the first element I, the fourth control input of the first prohibition element, the control inputs of the fifth, sixth and seventh prohibition elements and the information input of the eighth prohibition element, the outputs of the second element I, the third and fourth prohibition elements are connected respectively to the inputs the first element OR, the outputs of the third element AND, from the fifth to the eighth prohibition elements are connected respectively to the inputs of the second element OR, the outputs of the second prohibition element, the first and second el OR, the inverse output of the first element I. and the output of the first prohibition element are connected respectively to the outputs from the second to the sixth direct code to additional code converters. TI Table 1 table 2 7 5.3 & 3 ten T T fc / // 44 / f 45 Figz 5.2 6.2 5.1 6.1 u Have I  L / ten l 36 Schig.5 $ # 41, 81