SU794634A1 - Device for multiplying series code by fractional factor - Google Patents

Description

DEVICE FOR MULTIPLICATION OF SEQUENTIAL

(54) CODE FOR FUNNY COEFFICIENT

;

The invention relates to the field of computational technology and can be applied to multiply by a fractional coefficient a number represented by a sequential D1 binary quasicanonical modified code. A device 1} is known for multiplying by a coefficient comprising a pulse generator, an AND element, frequency dividers, counters, and a matching unit. However, it does not allow combining in time the processes of the bitwise input of the operand, the computation and the bitwise output of the result, which may be necessary if the operands at the input and output of the device are represented by a serial code (for example, in the case of restrictions on the number of external outputs when manufacturing the device). in the form of BIS). The closest in technical terms to the invention is a device in 2, containing a partial product register, coefficient code registers, two adders, and the result digit encoder; the control input of the first adder and the first and second inputs of the first adder bits are connected respectively to the input bus of the code multiplier, with the output of the bits of the register of partial product and the output of the bits of the register of the coefficient code, the output of the higher bits of the first adder is connected to the input of the decoder of the result digits, the output whose output is the output of the device. The first input of the bits of the second adder is connected to the output of the bits of the second register of the coefficient code, the control input of the register of partial output is the control input of the device. The functionality of such a device is limited, since the device allows to multiply the number by a fractional coefficient only if the denominator of the coefficient is an integer base degree of the number system. The aim of the invention is to expand the functionality of the device. The goal is achieved in that the device containing the partial product register, the coefficient code registers, two adders and the digit decoder of the result, when the control input of the first adder and the first and second inputs of the first adder bits are connected correspondingly with the input bus, the multiplicable code, with the output of the bits of the partial product register and the output of the bits of the first register of the coefficient code, the output of the higher bits of the multiplier ) the adder is connected to the input of the decoder of the result digits, the output of which is the output of the device result, the first input of the bits of the second adder is connected to the output of the bits of the second coefficient code register, the control input of the partial product register is additionally communications are entered; the output of the bits of the first adder is connected to the second input of the bits of the second adder, the control input and the output of the bits of which are connected respectively to the output d of the encoder of the result digits and the input of the bits of the partial product register. The drawing shows the scheme of the device. The device contains a register of 1 part product, the first 2 and second 3 registers of the coefficient code, adders 4, 5, a decoder 6 digits of the result, the input bus 7 of the multiplicand code. The 6-digit decoder of the result is a combinatorial circuit that implements the following logic functions f a () where the argument indices correspond to the number) of the bits of the adder 4, f and f2 with the digit values (respectively 1 and 1) of the result. The device works as follows. In the initial state (the setting chains of the initial state are not shown in the drawing), register 1 contains zeros in the first register 2 numerator L of the coefficient, and in the second register 3 the number 1-B, i.e. additional code is the denominator of the B coefficient. Values A and B satisfy the conditions 0 ,,

2

ABOUT

e

0001100000 00011 11101 0000011101

e

0000 UNI 1111 0001 11111110

0001100110 00001 11111 1111011003

.four

.0 1 o o o 1

001

000

111 011

.five

4 T

000

111

000

000 110 001

111

000 in each i-th calculation cycle, an operand digit X with a weight enters the input bus 7 of the multiplier code, (where p is the number of bits), after which the number is fixed in X. This digit controls the type of operation performed by the adder in this way that on adder 4, the contents of register 1 are added to the direct code of the contents of register 2, if the digit is plus one, and with the additional code, if the digit is minus one, and register 2 is not summed up, if this digit is zero. The decoder of the digits of the result b, analyzing the contents of the three most significant bits of the adder 4, generates the digit of the result U. Beli at the output of the specified bits 000 or 111, the digit of the result is zero, in other cases the digit of the result is equal to 1, and its sign is the code of the adder 4. The result digit is output from the device over the output bus 8 Chi in the manner described above for adder 4) and controls the type of operation performed by adder 5 where the addition of the direct or additional register code 3 with the adder code 4 occurs. CycleIt is replaced by a signal at control input 9, according to which the code of adder 5 is received into register 1. The device operates in a numerical example for the values A, 011 3/8, B, 111 7/8, X lOllOl 35 as shown in table 1, where the digit is obtained of the result 01011 15. As can be seen from the example, the proposed device allows to combine in time the processes of pore operative input of the operand and the output of the result when calculating the function y - K. However, unlike the prototype device, the proposed device does not require B 2, where c is a whole. Therefore, the proposed device can find wider application.

Claims (2)

1. USSR Author's Certificate No. 590735, cl. 6 F 7/39, 1976. 2. USSR author's certificate for application number 2441679 / 18-24, cl. G About F 7/39, 1977 (prototype).