SU805303A1 - Digital device for taking antilogarithms - Google Patents

Description

(54) DIGITAL DEVICE FOR POTENTIATION

The invention relates to computing and can be used as a digital generator of the exponential function and to build specialized and universal high-speed computing devices. A device for functional conversion is known, which contains the argument register, memory blocks, multipliers, and adder 1. The disadvantage of the device is a large amount of equipment. Most. close to the technical essence of the invention is a device for potentiating, containing the argument register, serially connected memory block, adder and result register I2j. The disadvantage of this device is the low accuracy of calculating the function e. The purpose of the invention is to improve the accuracy. The goal is achieved by the fact that the device containing the argument register, the memory unit and the successively connected adder and result register, the output of the memory unit is connected to the first input of the adder, a dividing unit and two comparison units are added, with the outputs from the first through -1) -and and c (K + 1) -th to n (where-n is the number of bits of the register of the argument) bits of the register of the argument are connected to the inputs of the first and second comparison blocks, respectively. The output of the K.-th register and register argument connected to control inputs the first and second comparison units, the outputs of which are connected respectively to the address input of the memory unit and the input of the divider of the division unit whose input of the dividend is connected to the output of the memory unit, the output of the division unit is connected to the second input of the adder. The value of the function e is calculated using the approximate formula pX 2 - x X where X x ,. + d X f А At the same time, the error is / R / 2 If the value of the parameter is k, which determines the highest K bits x, i.e. the value of xd is fixed, then formula (1) gives the ZK of the correct decimal places.

Set

if a . X 1 o

: 2)

Bo +. 2 if xix

tax if

Xk o

L z

their -2- if X

X ..

one

then X ZQ + 4Z, / 21.21, and the accuracy values of the formula (1) obtained above remain therefore valid when x is replaced by x and dx by D2. At the same time, the intermediate argument Zg takes significantly fewer different values, namely (1) values instead of 2 in the case of the argument Xd. For calculations, we obtain the final formula

gX,

-

(3)

2 - dg

To calculate by the formula (3), you can use the table of values, (Putting it in the corresponding memory block.

The block diagram of the proposed device shown in the drawing.

The device contains a register of 1 argument, a first comparison block 2, a memory block 3, a second comparison block 4, a division block 5, an adder b and a result register 7.

The device works as follows.

The output of the K-th bit of register 1 of the argument gives the value of the K-th bit of the argument X, namely X |, depending on which, in accordance with relations (2), comparison blocks 2 and 4 form the values ZQ and Lz. Unit 2 receives from the output of register 1 the value of the intermediate parameter, the argument Xd and, depending on the signal value at the control input, transmits the value KQ unchanged (x 0), or adds to the XQ code a K-th digit (x. 1) . Block 4, the input of which enters. The value of L X, forms the code value 2 dx (in the case of x 0) and the code of the value (2 + 2) - dx (in the case of x 1)

From the block 3 of the memory, by the argument z arriving at its input, used as the address of a constant in the block, the corresponding value is selected

. This value, shifted by two digits to the left, is fed to the input of the dividend divider 5, which corresponds to the value, and the input to the divider is 2 - dg. The adder 6 performs the subtraction of the constant e 0 from the output of memory block 3 from the output of the division block, equal to (dg), forming, in accordance with formula (3), the desired value of function e on the result register 7.

The volume of the memory block of the proposed device is equal to (1) constants, and the accuracy of the result of potentiation is equal to the GC of the binary bits of the fractional part of the result.

invention formula

0 A digital potentiator comprising a register of the argument, a memory block and a series-connected adder and a result register, the output of the memory block being connected to

5 with the first input of an adder, characterized in that, in order to increase accuracy, a dividing unit and two comparison units are additionally introduced into it, with the outputs from the first to (K-1) -th and from (K + 1) -th to n

(where n is the number of bits of the register of the argument) the bits of the register of the argument are connected to the inputs of the first and second blocks, respectively

C comparison, the output of the K-th bit of the argument register is connected to the control, inputs of the first and second comparison blocks, the outputs of which are connected respectively to the address input of the memory block and the input of the divider of the division block whose input is divisible and connected to the output of the memory block, the output of the division unit is connected to the second input of the adder.

Information sources,

5 taken into account in the examination

1. USSR author's certificate number 575647, cl. G 06 F 7/38, 1977.

2. USSR author's certificate according to the application 2401420 / 18-24,

cl. G 06 F 7/38, 1977 (prototype).

Claims (1)

Claim A digital device for potentiation, containing an argument register, a memory block and a series-connected adder and a result register, the output of the memory block being connected to the first input of the adder, which requires the addition of a division block and two comparison blocks, and the outputs from the first to (K-1) -th and from (K + 1) -th other η (where η is the number of bits of the argument register) bits of the register of the argument are connected to the inputs of the first and second comparison blocks, respectively, output K-th category reg the argument is connected to the control inputs of the first and second comparison blocks, the outputs of which are connected respectively to the address input of the memory block and the input of the divider of the division block, the input of which is divisible is connected to the output of the memory block, the output of the division block is connected to the second input of the adder.