SU1361545A1 - Division device - Google Patents

Abstract

FIELD: computation. It can be used as an approximate division unit. The purpose of the invention is J5 16/7 5 reducing the amount of equipment. The device contains two blocks 1, 6 of logarithm memory, two blocks 2, 7 of logarithm correction values, incrementor 3, multiplexer 4, element OR 5, two adders 8, II exponent memory block 9, exponential correction values memory block 10 and block 12 shift. The reduction in hardware costs is achieved by introducing two memory blocks of correction values of logarithms, an incrementor, a multiplexer, an OR element, an adder, a memory block of corrective values of the exponent, and original connections between nodes and blocks. 1 il. 5 73 1 20. G1 11. “A. i 21

Description

The invention relates to computing and can be used as an approximate division unit.

The purpose of the invention is to reduce the amount of equipment.

The drawing shows a diagram of the device.

The device contains block 1 of logarithms of memory, block 2 of memory of corrective values of logarithms, incrementor 3, multiplexer A, the element OR. 5, memory block 6 of logarithms, memory block 7 of correction values of logarithms, adder 8, memory block 9 of exponentials, memory block 10. Corrective values of exponentials, adder 11 and shift block I 2,

The inputs 13 of the dividend and the inputs 14 of the divider are the information inputs of the device. Inputs 15 t of the highest delimited bits are connected to the inputs of the higher bits of the SHSh 5 and. blocks 1 and 2 of memory, the inputs of 16 bits divisible from (1 + 1) -th to (1 + t) -th are connected to the inputs of the lower bits of the element OR 5 and the block 1 of memory, the inputs of 17 lower bits of the dividend, from (1 + ha + 1) -th to n-th are connected to the inputs of the lower bits of memory block 2. The high-order outputs of memory blocks 1 and 2 are connected respectively to the first and second groups of information inputs of multiplexer 4, the control input of which is connected to the output of the OR element 5. The 18 high-end splitter inputs are connected to the high-level inputs of memory blocks 6 and 7 These inputs of the 19 bits of the divider from (1 + 1) -th to (1 + t) -th are connected to the inputs of the lower bits of memory block 6, and the inputs of the 20 lower-order bits of the divider with (5-Hp + 1) - Go to p-th connected to the inputs of the lower bits of the memory block 7. The inputs of the first, second, third, and fourth terms of summator 8 are connected respectively to the low-order outputs of memory blocks 1 and 2 and to the outputs of memory blocks 6 and 7. The transfer output of the adder 8 is connected to the control input of the encoder 3, the information inputs of which are connected to the codes of the multiplexer 4. The outputs 1 of the higher bits of the adder 8 are connected to the inputs of the higher bits of memory 9 and 10, the outputs of the bits of the adder 8 s ( 1 + 1) - th (1 + t) th - to the junior inputs

The bits of the memory block 9 and the low-order bits from (1n-t + 1) -th through the n-th to the inputs of the lower bits of the memory block 10. The outputs of memory blocks 9 and 10 are connected respectively to the inputs of the first and second terms of the adder 11, the outputs of which are connected to the information inputs of the shifter 12, the control inputs of which are connected to the outputs of the incrementor 3. The outputs 21 of the shifter 12 are the information outputs of the device.

The device works as follows.

The division is realized by the formula

A / B 2

eo (j; j, 4-feg-2a;

(one)

The dividend A is fed to the inputs of blocks 1 and 2, which contain the characteristic and the mantissa of the corresponding logarithm values. Depending on the values of the older, middle and lower-order bits of divisible A, the incrementor 3 through multiplexer 4 receives the characteristic of the logarithm from block 1 (in the case of at least one bit in the older and middle digits of the splittable A, determines the formation of a control signal by the element of RShI 5 for multiplexer 4 (or from: block 2) at zero value of the high and middle bits of the dividend A). The values of the mantis sy logarithms and correction functions from the outputs of blocks 1, 2, 6 and 7 are fed to the inputs of the adder 8, where the function

40

F (x) F, (x) - F2 (x); (2) Fi (x) f (xe,) + 1, (xe. „), (3)

where f. (Xj) is the value of the function at the nodal points; the value of the corrective function.

. (", T)

F., (x) F (x).

If, when performing (2) in the adder 8, a transfer occurs, a control signal is generated for the incrementor 3, which increases by one least significant bit the value of the characteristic of the dividend A. The obtained value of the mantis difference of the logarithms (2) goes to the inputs of blocks 9 and 10, which together with the adder 11 implement the calculation of the exponent according to (1) and (3). At the exits.

adder 11 sets the value of the quotient of the division of the normalized divisible and divisor. Since the divisible A is not normalized, the value of the quotient at the outputs of the adder 11 must be shifted to the right in the shift block 12 by the number of bits determined by the value of the integer part of the logarithm of the quotient. The value of the private C from the division of the divisible A and the divider B is set at the outputs of the shift block 12 in time Ta, defined by

by

Td. 2t, + 3t + 2 t ,.

(four)

The total memory capacity of blocks 1, 2, 6, 7, 9 and 10 is defined as

. Q (2N + E, t log, N}) + (2P, + E, tUog, .N.2 .P,

where P is the corrective magnitude

functions; N is the operand width;

1 1 is the bit width of the address inputs 1. Respectively of the groups of senior middle and junior bits of blocks 1,2,6 and 7;

1, t „,

 2-bit address inputs

1, respectively, of the groups of the senior, middle, and junior bits of blocks 9 and IO.

Claims (1)

Invention Formula A device for dividing, containing two logarithm memory blocks, a first adder, an exponential memory block and a shift block, whose bit outputs are device outlets, the bits of the first to (T + ha) divisible device bits (1, m - integers) are connected to the corresponding inputs of the first memory block of logarithms, the inputs of the divider bits of the device from the first to (1 + t) th are connected to the corresponding inputs of the second memory block of the logarithms, the outputs of the young Our bits of the first memory block of logarithms and the outputs of the bits of the second memory block of logarithms are connected to the inputs of the first adder, the outputs of which bits from (1 + 1) to five five 0 five 0 .. v five (1 + t) th is connected to the corresponding inputs of the exponent memory block, characterized in that, in order to reduce the number of equipment, it contains two memory blocks of correction values of logarithms, a memory block of correction values of exponentials, the OR element, multiplexer, incrementor and the second adder, the inputs of the discharge unit from the first to (1 + t) are connected to the inputs of the 1-SHI element, the output of which is connected to the control input of the multiplexer, whose information inputs are connected to the outputs of the higher first-order bits the logarithm memory block and the first memory block of the logarithm correction values, respectively, the inputs of the bits of the divisible device from the first to the Bth and from (1 + m-I) -th to the n-th (n is the operand width) are connected to the inputs the first memory block of the correction values of the logarithms, the inputs of the bits of the device divider from the first to the 1st and from (1 + t + 1) -th to the nth are connected to. the inputs of the second memory block of correction values of logarithms, the low-order bits of the first memory block of correction values of logarithms and the bits of the second memory block of correction values of logarithms are connected to the inputs of the first adder, the overflow output of which is connected to the control input of the incrementor, information the inputs of which are connected to the outputs of the multiplexer bits, and the outputs are connected to the control inputs of the shift unit, the information inputs of which are connected to the outputs of the bits second the adder, the inputs of the bits of which are connected to the outputs of the corresponding bits of the exponential memory block and the memory block of the correction values of the exponentials, the outputs of the bits of the first adder from the first to the 1st block are connected to the corresponding inputs of the block of the exponents and the memory block the correction values of the exponents, the outputs of the bits of the first adder with (1 + t + +1) -th to the n-th are connected to the inputs of the memory block of the correction values of the exponentials.