JP2580413B2 - Multiplication processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed multiplication device suitable for LSI, and more particularly to a multiplication device for recoding a multiplier to generate a partial product.

[0002]

2. Description of the Related Art By performing rounding on a result of multiplication, accurate multiplication can be performed repeatedly. For example, consider a repetitive multiplication that takes in the multiplication result as the operand of the next multiplication. At this time, if the number of digits that can be input to the multiplier is n, the multiplication result is n or more. When the multiplication result of n or more digits is truncated to n digits and input as the operand of the next multiplication, the input operand value is set to 1 as the weight of the least significant digit of the truncated operand compared to the multiplication result before truncation. For example, an error of less than 1 appears. On the other hand, when the closest rounding process is executed and the result is input as an operand, the error is reduced to half at the maximum. That is, when the closest rounding processing is performed, the operand input to the next multiplication is more accurate than when the operand is truncated, so that iterative multiplication with high precision is possible.

A conventional example for realizing a repetitive multiplication that executes a rounding process for each multiplication will be described below. FIG. 9 shows a block diagram of an iterative multiplication processing apparatus that conventionally performs a rounding process for each multiplication. Reference numeral 901 denotes a selection latch, and reference numerals 902, 903, 904, and 905 denote latches, which are operated by two-phase clocks ph1 and ph2. Reference numeral 906 denotes 2 latched by the selection latch 901
Divide the multiplier of the radix into a set of 2 bits from the lower digit,
A 2-bit Booth recoding circuit that recodes each set to a value between -2 and 2. 907 is a latch 902
Multiplied and 2-bit booth recode circuit 9 latched in
This is a partial product generation and addition circuit that generates and adds a partial product using the recoded value output from the output unit 06 and outputs the addition result to the latch 903 in the form of, for example, an intermediate result of a redundant binary number. 9
Reference numeral 08 denotes a binary conversion circuit that converts a redundant binary number into a binary number. 909 is converted by the binary number conversion circuit 908 into 2
This is a rounding circuit for rounding a multiplication result converted to a base number to a certain digit.

Using the multiplication processing device shown in FIG. 9, for example, multiplication as shown in equation (1) is executed. P _n = P _n-1 × Q _n-1 (1) First, P _n-1 is input to the selection latch 901 as a multiplier, and Q _n-1 is input to the latch 902 as a multiplicand. . The multiplication shown in the expression (1) passes through a 2-bit Booth recode circuit 906 and a partial product generation addition circuit 907 and is taken into a latch 903 as an intermediate result of a redundant binary number.
In the next cycle, the intermediate result is latched by the latch 904 and converted to a binary number by the binary number conversion circuit 908. After that, the data is rounded to a digit which is a rounding circuit 909,
The signal is input to the latch 905. Then, the result of the rounding process in the next cycle is input to the selection latch 901, and the next multiplication P _n × Q _n is executed. At this time, the latch 902, it is assumed that the data Q _n are incorporated. That is, in the conventional repetitive multiplication in which the rounding process is performed for each multiplication, the binary conversion circuit 908 and the rounding circuit 909 are used for each multiplication.

Next, a description will be given of a conventional example in which a value obtained by subtracting a multiplier from a certain constant A is multiplied by a multiplicand, and repetitive multiplication is performed using the multiplication result as a multiplier of the next multiplication. FIG. 10 shows a conventional multiplication processing device. In FIG.
The same blocks as those used in FIG. 9 have the same numbers. A subtraction circuit 1001 subtracts a numerical value selected by the selection latch 901 from a constant A.

Hereinafter, the operation of the multiplication processing apparatus shown in FIG. 10 when iteratively performing multiplication as shown in equation (2) will be described. P _n = (A−P _n−1 ) × Q _n−1 (2) In the first cycle, P _n−1 is input to the selection latch 901 as a multiplier, and (A−P _n−1 ) P _n-1 )
Is executed and input to the 2-bit Booth recode circuit 906. On the other hand, Q _n-1 is input to the latch 902 as the multiplicand, and the partial product generation and addition circuit 907 performs generation and addition of the partial product using the multiplier recoded value, thereby generating an intermediate result of, for example, a redundant binary number. This intermediate result is the result of latch 903
It is taken in. In the second cycle, the intermediate result is latched by the latch 904 and converted to a binary number by the binary number conversion circuit 908. Then, the rounding circuit 909 performs rounding processing with significant digits, and performs a binary multiplication result ((A−P _n−1 ) ×
Q _n-1 ) is latched in the latch 905. In the third cycle, the selection latch 901 selects the result of the multiplication in the previous cycle, and executes the multiplication in the same manner as in the first cycle. Thereafter, the operations of the second cycle and the third cycle are repeated, and the binary multiplication result is output in the n-th cycle (n is an even number).

As described above, in a repetitive multiplication in which a value obtained by subtracting a multiplier from a constant A and a multiplicand and the multiplication result is a multiplier of the next multiplication, the multiplier is subtracted from the constant for each multiplication. A subtraction circuit was used.

FIG. 13 is a block diagram of a conventional multiplication apparatus for multiplying a multiplicand by a value obtained by subtracting an intermediate product (redundant binary number) obtained by a previous multiplication from a certain constant A. . Reference numeral 1301 denotes a selection latch for selecting a redundant binary number and a multiplier and latching the same with a clock ph1. Latches 1302, 1303, 1304, and 1305 operate at clocks ph1 and ph2, respectively. 1
306 is a redundant binary 2-bit Booth recode circuit 130
This is a partial product generation circuit that generates and adds a partial product based on the output value of 7 and the output of the latch 1302, and outputs a redundant binary intermediate product. 1307 is a redundant binary number addition / subtraction circuit 131
This is a redundant binary 2-bit Booth recode circuit that groups output values of 0 into groups of two digits from the bottom, and recodes them into values of −2 to 2, respectively. Reference numeral 1308 denotes a binary conversion circuit for converting a redundant binary intermediate product output from the latch 1304 into a binary multiplication result. Reference numeral 1309 denotes a rounding circuit for rounding and normalizing the multiplication result output from the binary number conversion circuit 1308. 1310 is a selection latch 1
This is a redundant binary addition / subtraction circuit for adding a redundant binary number to a redundant binary value latched at 301 and a constant A. However, when a binary number is input to the redundant binary number addition / subtraction circuit 1310, a certain constant A is set to 0.

Next, the operation of multiplying the multiplicand by a value obtained by subtracting the intermediate product (redundant binary number) obtained by the previous multiplication from a certain constant A using the multiplication processing apparatus shown in FIG. 13 will be described. In equation (2), P _n-1 is a redundant binary intermediate result obtained as a result of the multiplication in the previous cycle. This intermediate result is input to the redundant binary number addition / subtraction circuit 1310 by the selection latch 1301. Together, redundant 2
A constant A is input as the other input value of the radix addition / subtraction circuit 1310. Here, (A−
P _n-1 ). At the same time, the multiplicand Q _n−1 is input to the latch 1302, and the multiplication (A−P _n−1 ) × Q
_n-1 is executed.

In the above-described multiplication processing apparatus for repeatedly multiplying the multiplication result in the form of an intermediate result in the previous cycle, a redundant binary number addition circuit is required to subtract the multiplication result of the previous cycle from a constant A. Had become. For this reason, there has been a problem that the execution speed of the multiplication becomes slow and the amount of hardware increases.

In the above three conventional examples, the case where the intermediate result is a redundant binary number which is one of the signed digits is described. However, a multiplication circuit or the like which outputs the intermediate result in the form of carry-save is described. The same configuration applies to a repetitive multiplication circuit that handles high radix.

[0012]

In a conventional iterative multiplication processing device which performs a rounding process for each multiplication, as described above, a binary conversion circuit and a rounding circuit are used for each multiplication to convert an intermediate result. It must be converted to a binary number and rounded. Therefore, there is a problem that the repetition multiplication speed is slow, the circuit scale is large, and the power consumption is also increased. Further, in a conventional repetitive multiplication in which a value obtained by subtracting a multiplier from a certain constant A and a multiplicand and the multiplication result is a multiplier of the next multiplication, as described above, a subtraction circuit is used for each multiplication to use a constant. Must be subtracted from the result of the multiplication. Therefore, there is a problem that the repetition multiplication speed is slow, the circuit scale is large, and the power consumption is also increased.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a multiplication processing apparatus suitable for repetitive multiplication at high speed, with a small circuit scale, and with low power consumption.

[0014]

According to the invention of claim 1 of the present application, an M-digit numerical value of a radix Υ is divided into a continuous set of N digits (M> = N), the set is input, and the set Numeric value of Zgi
A plurality of intermediate sum intermediate carry generating means for dividing the intermediate sum into an intermediate carry Si and an intermediate carry Ci, and a recode value generating means for adding the intermediate sum Si and an intermediate carry Ci-1 from a set one level lower than the intermediate sum Si And a selection circuit for selecting one of a plurality of numerical values in the same format as the intermediate carry Ci and inputting the selected value as an intermediate carry Ci-1 from one subset of the recode value generating means. And a partial product generation and addition circuit for generating and adding a partial product with the multiplicand based on the recode value output from the recode value generation means and outputting the product to the recode circuit.

According to a sixth aspect of the present invention, in the multiplication processing apparatus of the first aspect, the intermediate sum intermediate carry generating means divides the radix-2 signed digit number into a continuous two-digit set, and significant digit using the signal Q _i-1 from one subset and a signal Q _i that it is 1, the set value Zg _i Z of
According to g _i = 4 × C _i + S _i , the data is divided into an intermediate sum S _i and an intermediate carry C _i , and further, R _i = S _i + Q _{i -1} and B _i = C _i.
+ Q _i bar to generate a second intermediate sum R _i and a second intermediate carry B _i , and the recode value generation means includes a second intermediate sum R _i and a second intermediate sum R _i from a subset. Using an intermediate carry B _i−1 , Z _i = C _i−1 + S _i = B _i−1 + R _i −
1, wherein the recoding value Z _i is calculated.

According to a seventh aspect of the present invention, in the multiplication processing device of the first aspect, the digit having the weight of 2-i has a non-zero value, and the lower order from the digit having the weight of 2- (i + 1). From a constant A expressed by a binary number which is 0, a certain numerical value B expressed by a redundant binary number (however, when the numerical value B is converted into a binary number, Bb
It is equal to ± α · 2-m. Here, Bb is a constant having a non-zero value in a digit having a weight of 2-m and a lower order being 0 from a digit having a weight of 2- (m + 1). A multiplication processing device for subtracting a number 1 ≦ α <2, i, m <j) and inputting the result to a recoding circuit, where L is the larger value of i and m; A higher value from 2-L of A-Bb is set up to the 2nd digit, and a numerical value 0 is set up from the 2- (L + 1) th digit to the 2- (k) th digit (L ≦ K ≦ j−1), 2 The-(k + 1) digit is the value of the 2- (k + 1) digit of the numerical value B if the value of the 2- (k) digit of the numerical value B is other than the numerical value 0, and the sign-inverted value of the numerical value B if the numerical value is 0 And input selection means for setting the sign-inverted value of the 2- (k + 2) -th digit or less of a certain numerical value B to all digits below the 2- (k + 2) -th digit and using the inverted value as an input to the recode circuit. It is characterized by the following.

[0017]

According to the first aspect of the present invention, by inputting a numerical value selected by the selection circuit as a carry from the lower part of the recode circuit, the carry value from the lower part of the recode circuit and a carry from the lower part are input. Recode the numerical value obtained by adding the numerical values. Thus, in the multiplication processing device, the multiplication of the multiplicand and the numerical value obtained by adding the input value of the recoding circuit and the carry value from the lower order is performed. According to the seventh and ninth aspects of the present invention, a constant B is subtracted from the constant A by providing input selection means, and the result is input to a recoding circuit so that multiplication can be performed repeatedly. In this case, there is no need to provide a subtraction circuit, and the multiplication process can be performed at high speed.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a description will be given of an arithmetic circuit for performing repetitive multiplication in which an intermediate result is rounded by a recoding circuit for each multiplication, according to one embodiment of the present invention. FIG. 1 is a block diagram of a multiplier recoding circuit and a carry generation circuit when the intermediate result X of the multiplication is input as a multiplier. The basic unit 101 of the multiplier recode circuit is a circuit that divides the multiplier X into sets of two digits and recodes the set. The intermediate sum intermediate carry generation circuit 10
2 and a recode value generation circuit 103. The intermediate sum intermediate carry generation circuit 102 sets the number of inputs X _{i + 1} , X _i to the j-th set and sets the value of this set to Zg _j , according to Zg _j = 2 ² × C _j + S _j . This is a circuit for dividing into an intermediate sum S _j and an intermediate carry C _j . Recode value generating circuit 103 adds the intermediate carry C _j-1 from the set of intermediate sum S _j and one lower previously described, is a circuit that generates a recoded value Z _j. The selection circuit 104 includes the 0 value generation circuit 10
This circuit selects a numerical value corresponding to C _j = 0 output from 5 and a carry by rounding output from the round carry generating circuit 106. The 0-value generation circuit 105 outputs the intermediate carry C input to the basic unit 101 of the multiplier recoding circuit.
_This is a circuit for generating a numerical value corresponding to _j-1 = 0. Rounding carry generating circuit 106, X _i of decimal values (X _i, X
_i-1 , X _i-2 ...), and generates a carry due to the nearest rounding in accordance with the format of the intermediate carry C _j-1 .

FIG. 2 is a block diagram of an iterative multiplication circuit when the circuit shown in FIG. 1 is used. 201 is a selection latch, and 202, 203, 204 and 205 are latches, respectively. Each latch is a two-phase clock ph
1, ph2. Multiplier recode circuit 207,
The carry generation circuit 210 is the circuit shown in FIG. 2
Reference numeral 06 denotes a partial product generation / addition circuit that generates and adds a partial product using the multiplicand latched by the latch 202 and the recode value output from the multiplier recode circuit 207, and outputs the result as an intermediate result. Reference numeral 208 denotes a binary number conversion circuit that converts the intermediate result into a binary number. 209 is a binary number conversion circuit 20
This is a rounding circuit for rounding the multiplication result converted into a binary number by 8 to a certain digit.

Next, using the circuits shown in FIGS. 1 and 2,
Consider performing the repetitive multiplication shown in equation (1). First, it is assumed that P _n-1 is input to the selection latch 201 as a multiplier, and Q _n-1 is input to the latch 202 as a multiplicand. The multiplication represented by the expression (1) passes through the multiplier recoding circuit 207 and the partial product generation addition circuit 206 in FIG. 1 and is taken into the latch 203 as an intermediate result. At this time, the multiplier recode circuit 207 selects and inputs the output value of the 0 value generation circuit 105 as a carry from the lower order.
In the next cycle, the intermediate result P _n−1 × Q _n−1 is latched by the selection latch 201 and recoded by the multiplier recode circuit 207. At this time, the selection circuit 104 selects the output value of the round carry generation circuit 106 as the carry from the lower order. Thus, in the recode circuit 207, carry by rounding and addition of a value higher than the digit to be rounded are realized by the recode circuit. That is, the intermediate result P _n-1 × Q
_{When n-1} is input to the multiplier recode circuit 207, it is recoded and rounded at the same time. At the same time, Q _n is input to the latch 202, and the next multiplication P _n × Q
_n is executed. When the binary result is finally obtained after the repetitive multiplication is performed several times, the intermediate result is taken into the latch 204, converted by the binary number conversion circuit 208, and then rounded by the rounding circuit 209. And a binary result is obtained.

As described above, in this embodiment, the multiplication is repeatedly performed using the intermediate result of the multiplication, and the intermediate result is rounded by the multiplier recoding circuit, whereby the multiplication is repeatedly performed at high speed. doing.

Next, a first embodiment using the present invention will be described.
This will be described with reference to FIG. FIG. 3 shows a 2-bit booth recoding circuit according to an embodiment of the present invention when the input is a redundant binary number. It is assumed that the redundant binary value X of each digit is coded with 2 bits (Xp, Xm) as shown in (Table 1).

[Table 1]

In (Table 1), (Xp, Xm) = (1, 1)
Is prohibited. The basic unit 301 of the redundant binary number 2-bit Booth recode circuit is a circuit that receives a continuous two-digit redundant binary number and recodes it into a numerical value from -2 to 2. The selection circuit 302 calculates 1 from two input binary numbers.
This is a circuit for selecting two binary numbers. The round carry generation circuit 303 is a circuit that generates carry by rounding using input data. The 0-value generation circuit 304 outputs a B _j-1 bar such that the carry from the lower digit of the basic unit 301 of the redundant binary 2-bit Booth recode circuit becomes “0”.
This is a circuit for generating the Q _j-1 bar. This is to set the carry from the lower digit of the recoding circuit to "0" in the first cycle of the repetitive multiplication. That is, in the embodiment shown in FIG. 3, X is used as a carry from the lower end of the basic unit 301 of the redundant binary 2-bit Booth recode circuit.
_i (Xp _i , Xm _i ) The carry value due to rounding generated to round to the digit (the output value of the round carry generation circuit 303).
Or a value “0” (the output value of the 0 value generation circuit 304) is selected and input using the selection circuit 302. Hereinafter, the configuration of each part described above will be described.

Basic unit 3 of 2-bit booth recoding circuit
FIG. 4 shows a truth table for constructing 01. However X _i, X _{i + 1:} Number of inputs Q _j: X _{i + 1} is _{"1" Q j-1:} X i-1 is "1" C _j: intermediate carry S _j: intermediate sum B _j: C _{j + Q j R j: S} j + Q j-1 bar X _i, X _{i + 1} is, 2 ⁱ digit of the input value X, which is 2 ^{i + 1} digit values. The set of (X _i , X _{i + 1} ) is the j-th set, and the value of this set is Zo _j . As a first means for recoding, the j-th set is divided into an intermediate carry C _{j from} this set and an intermediate sum S _j of this set. However, the intermediate carry C _j is a value from -1 to 1,
The intermediate sum _Sj takes a value from -2 to 2.
Then, the relationship between Zo _j , C _j and S _j is as shown in equation (3). _{^{Zoj = 2 2 × C j +}} S j = 4 × C j + Sj ··· (3) for _{example, Zo j = 3 ((X} i + 1, X i) = (1,1))
In the case of (C _j , S _j ) = (1, −1). _{However, Zo j = 2, -2 (} (X i + 1, X i) = (1,
0), (−1, 0)), there are two ways of taking the combination of (C _j , S _j ), so that the combination is not uniquely determined as described above. In this case, the determination is made based on the carry information from the lower group. Q _j is a signal indicating that the value of the upper digit (X _{i + 1} ) in the j-th set is “1”. That is, referring to FIG. 4, Q _j = 1 corresponds to C _j from the set.
Indicates that “1” or “0” rises to a higher set. Further, Q _j = 0 indicates that “0” or “−1” increases as C _j . For _{example, Zo j = -2 ((X} i + 1, X i) =
(-1, 0)), (C _j , S _j ) = (0, −
2) and (−1, 2). Q _j-1 =
In the case of 1, since C _j-1 = 0 or 1, S _j is a negative value, and (C _j , S _j ) = (0, -2) is adopted. As a result, C _j-1 can be obtained by the following second means.
The added value of + S _j does not exceed the numerical range from -2 to 2. Thus, (C _j , S _j ) is determined for all cases using Q _j-1 from one subset.

However, as it is, C _j (−1 to 1)
, And a 3-bit signal are required to represent S _j (−2 to 2), which complicates the circuit. In order to simplify the circuit, as shown in equation (4), instead of the intermediate carry C _j , B _j and the intermediate carry S _{j are used.}
Use R _j instead of

(Equation 1)

When B _j and R _j are obtained according to the equation (4), as shown in FIG. 4, B _j is 0 or 1, R _j is 2, 1, and
0 and -1. That is, B _j is 1 bit, R _j is
Is represented by 2 bits, C _j, circuit can be simplified compared with the case of using S _j. Here, R _j is assigned using R1 _j and R2 _j as shown in (Table 2).

[Table 2] Then, as it follows from the truth table of FIG. 4, B _j, R
1 _j , R2 _j and Q _j are obtained. Hereinafter, ◎ indicates an exclusive OR operation.

(Equation 2)

Next, as a second means of the recoding, the addition of the intermediate sum S _{j of} each set and the carry C _j-1 from the lower set is executed. Assuming that the result after recoding is Z _j , equation (9) is used using equation (4). Z _j = C _j-1 + S _j = B _j-1 + R _j -1 (9) From the equation (9), the relationship between Z _j , B _j-1 and R _j is shown in (Table 3).

[Table 3]

[0028] than (Table 3), Z _j is to take a value from -2 to 2, representing a Z _j in 3-bit value. Z _j
Zs _j , Z1 _j , and Z2 _j are represented by three bits (Table 4).
Assign as shown.

[Table 4]

[0029] Z1 _j, the absolute value of Z _j is "1", Z2 _j
Indicates that the absolute value of Z _j is “2”, and Zs _j indicates the sign of Z _j . From the above, the result Z _j (Z1 _j , Z2 _j ,
Zs _j ) is expressed as in equation (10) using B _j−1 , R _j (R1 _j , R2 _j ).

(Equation 3) Thus, the basic unit 301 of the redundant binary 2-bit Booth recode circuit shown in FIG. 3 is configured by using the equations (5), (6), (7), (8), and (10).

As described above, the redundant 2 shown in FIG.
The basic unit 301 of the binary 2-bit Booth recode circuit is:
The intermediate sum intermediate carry generating means generates an intermediate sum S _j (R _j ) and an intermediate carry C _j (B _j ) based on the information of carry Q _j-1 from the next lower set, The intermediate carry C _j-1 (B _j-1 ) from the next lower set by the recode value generating means
And the intermediate sum S _j (R _j ) are added to obtain a recoded value. That is, if the carry by rounding is input as the intermediate carry C _j-1 (B _j-1 ) from the next lower set in the recode value generating means, a redundant binary 2-bit booth is obtained as a rounded multiplier. This means that it has been input to the recode circuit 301.

Next, the round carry generation circuit 303 will be described. Here, it is assumed that the closest rounding based on the IEEE 754 standard is executed. Assuming that the input value X is rounded to 2 ⁱ digits, according to the IEEE 754 standard, the relationship between carry by rounding and the input value is as shown in FIG. Here, X _i and X _i-1 are 2 ⁱ digits and 2 ^{i of the} input value X, respectively.
^{It is an i-1} digit redundant binary value. X _i−2 is a sticky digit, and 2 ⁱ⁻² or less is “positive” or “negative”
0 ”. If it is positive, X _i−2 =
1, if negative, X _i−2 = −1, if zero, X _i−2
= 0. Cr _j-1 is a carry from X _{i -1} to X _i that occurs when X _i-1 and X _i-2 are rounded. IEEE
According to E754 standard, carry Cr by nearest rounding
_j-1, when a 1 weight digit of X _i, is distinguished by either lower digit than X _i is how much compared to the weight of the X _i digit is as follows.

When the digit lower than X _i > 1/2, Cr _j−1 = 1 1/2> The digit lower than X _i > −1/2, from Cr _j−1 = 0 −1/2> X _i When the lower digit is Cr _j-1 = -1 X _{i When the} lower digit is 1/2 with respect to the weight of X _i digit, X
Cr that rounds to _i digits and then becomes the nearest even number
_j-1 . For example, (X _i−1 , X _i−2 ) = (− 1, 0)
Of the time, the lower digit than X _i is against the weight of the X _i digit -1/2
Since it is, the Cr _j-1 = -1 when X _i = 1 when _{Cr j-1 = -1, Cr} j-1 = 0 when _{X i = 0, X i =} -1. That is, according to the redundant binary coding shown in (Table 1), Cr _j-1 = − (Xp _i + Xm _i ). In other cases, Cr _j-1 can be similarly obtained using the above rules.

Next, the carry Cr _j-1 due to the rounding is converted to the carry C _j-1 (B _j-1 , Q _j) from the lower order of the basic unit 301 of the above-described redundant binary 2-bit booth recoding circuit.
_j-1 ) coded for input. In FIG. 4, when the relationship between C _j , Q _j , and B _j is determined, the relationship is as shown in (Table 5).

[Table 5] According to (Table 5), carry Cr _j-1 by rounding is
FIG. 5 shows a representation using Q _j-1 and B _j-1 .
At this time, if Cr _j-1 = 0, there are two ways of taking (1, 0) and (0, ₁ ) as (Q _j-1 , B _j-1 ).
Here, it is set to be the same as Q _{j in} the recoding circuit of the redundant binary 2-bit booth. That is, X _i-1
Is "1", Q _j-1 = 1.

As described above, carry Cr _j-1 by rounding
Is obtained from Q _j-1 and B _j-1 as shown in equation (11) from FIG.

(Equation 4) As described above, the round carry generation circuit 30 shown in FIG.
3 can be configured. Rounding carry generation circuit 303
Is gate - is constituted by preparative number of delay stages is three stages, to become the same as the number of delay stages for obtaining the B _j redundant binary 2-bit Booth recoding circuit 301, the addition of the rounding carry generating circuit 303, a redundant It hardly slows down the speed of finding the binary 2-bit Booth recode value.

The 0 value generation circuit 304 is a circuit for generating "0" as a carry. This is from (Table 5)
Consider the case where C _j = 0, and (B _j , Q _j ) =
Since it is (1, 0) or (0, 1), as shown in FIG. 3, the logic may be such that B _j and Q _j are always in the form of logical inversion, and the 0 value can be generated at high speed. I understand.

From the above, the redundant binary 2-bit Booth recode circuit shown in FIG. 3 is formed, and when it is used to form a repetitive multiplication circuit, the circuit is as shown in FIG. That is,
The repetitive multiplication circuit using the present invention can perform high-speed repetitive multiplication by rounding a multiplication result without using a binary conversion circuit and a rounding circuit in the middle of repetition multiplication.

Next, as a second embodiment, a description will be given of a repetitive multiplication in which carry-save data is used at the time of repetition of multiplication. The configuration of the multiplication processing device that repeatedly performs the multiplication in the carry-preserving form has the configuration of the repetition multiplication shown in FIG. 2, as in the case of the redundant binary number. Here, a multiplier recode circuit to which carry-save data can be input will be described. Intermediate product X expressed in carry-save form
The recoding of (Xc, Xs) is performed in two steps. The i-th digit after the decimal point of the intermediate product is 2 having a weight of 2 ⁱ
It is assumed that the bits are represented by bits Xc _i and Xs _i . Where X
c _i and Xs _i are numerical values of 0 or 1. First, the intermediate product X
Is divided into adjacent two-digit groups.

(Step 1) In step 1, in each group, 4 · C _j + S _j = 2 · (Xc _{2i + 1} + Xs _{2i + 1} ) +
In order to satisfy (Xc _2i + Xs _2i ), the intermediate carry C _j ,
Find the intermediate sum _Sj . Here, the intermediate carry C _j is “0,
One of the four values of 1, 2 ", the intermediate sum _Sj is"-
The value is any one of five values of 3, -2, -1, 0, and 1 ". A table showing this value is shown in (Table 6).

[Table 6]

(Step 2) In step 2, in each group, the intermediate result S _j obtained in step 1 and the intermediate carry C _j-1 from the lower digit are added to obtain a recoded multiplier value Re _j . . Here, Re _j is “−2, −1, 0,
1, 2 ". Therefore, at this time, C
_j-1 + _Sj must be in the range of ± 2. For this purpose, in step 1, in each group, the upper digit (Xc _2i-1 ) of one lower group is examined together with the two digits of the group, and C _j and S _j are determined as shown in Table 6. For example, (Xc _{2i + 1} , Xs _{2i + 1} , Xc _2i , X
For s _2i) = (0,0,0,1), as-taking from a value "1" with the this group, C _j, S _j,
(C _j , S _j ) = (1, -3) and (0, 1).
Here, attention is paid to Xc _{2i + 1} . When Xc _{2i + 1} is 0, C _j always becomes a numerical value of 0 or 1. Xc _{2i + 1}
Is 1, C _j always becomes a numerical value of 1 or 2.
Therefore, when looking at one lower group, Xc _2i-1
Is 0, the carry from the lower group must be C _j-1
0 or 1 comes up. In this case, (C _j ,
If S _j ) = (1, -3), step 2
When Re _j = C _j-1 + S _j is executed, Re _j = −3
Or −2, and the range of Re _j described above (−2 to 2)
Out of range. Conversely, (C _j , S _j ) = (0,
If 1) is set, Re _j = 1 or 2, and the above condition is satisfied. Thus, all C _j and S _j are determined by looking at one lower group, Xc _{2i + 1} . Next, in step 2, a recoded value is generated in accordance with Re _j = C _j-1 + S _j . Table 7 shows this logic, that is, Re _j for C _j-1 and S _j .

[Table 7]

As described above, when recoding a carry-preserving number, as in the case of a redundant binary number, an intermediate carry and an intermediate sum are generated as step 1, and an intermediate carry from one lower group is generated as step 2. The carry and the intermediate sum of the group are added to obtain a recoded value. Therefore, similarly to the case where a redundant binary number is used as an intermediate product, if the result of the rounding process is input as an intermediate carry from the lower end of the multiplier recoding circuit of the lowest group, the rounding process can be similarly realized. Is clear. That is, a repetitive multiplication circuit using a carry-preserving type numerical value can be realized without using a binary number conversion circuit and a rounding circuit in the middle of repetitive multiplication, and it is possible to perform high-speed repetitive multiplication for rounding a multiplication result.

Next, as a third embodiment, repeated multiplication in the case where a binary number is used at the time of repeating multiplication will be described. Normally, the n-digit binary multiplier value X is recoded as shown in equation (12).

(Equation 5) Here, _assuming that Z _2j is (−2 × X _{2j + 1} + X _2j + X _2j−1 ), Z _2j is the j-th 2-bit Booth recoded value counted from the lower set. At this time, a truth table of the 2-bit Booth recode circuit is shown in (Table 8). X _{i + 1} , X _i , X
_i-1 is a multiplier input value. The 2-bit Booth recoded value Z _j is represented by a 3-bit signal (Zs _j , Z1 _j , Z2 _j ).

[Table 8] This logical expression is, for example, as shown in Expression (13).

(Equation 6)

When Expression (13) is expressed using a gate,
The basic unit of the binary 2-bit Booth recode circuit is as shown by 601 in FIG. That is, it can be seen that the recode value can be obtained with two gate delay stages at the most when data is input. Here, a case is considered in which a value exists in data of 2 ^i-1 digit or less, and this value is rounded to 2 ⁱ digits. When rounding up 2 ⁱ digits, 2 when ⁱ carry caused to round up digits and Cr _j-1, the sum of 2 ⁱ values with the digit carry by rounding Cr _j-1 and X _i (X _i + Cr
_j-1 ). Therefore, the recoded value Z of the lowest set
_i becomes as shown in equation (14). Z _i = −2 × X _{i + 1} + (X _i + C _i−1 ) = − 2 × X _{i + 1} + X _i + C _i−1 (14) That is, as shown in the equation (14), recoded value Z _i in the case of rounding up 2 ⁱ digits, simply it can be seen that may be input carry Cr _i-1 by rounding instead of X _i-1. Therefore, as in the first embodiment, the carry caused by rounding _{X i + 1, X i,} X of a circuit for recoding the X _i-1
When inputting to the input of _i-1 and there is no need to perform the rounding process, "0" may be input to the input of Xi _-1 .

FIG. 6 shows the configuration of the multiplier recode circuit and the carry generation circuit. 602 is an output value of the round carry generation circuit 603 according to the select signal;
This is a selection circuit that selects and outputs one of the outputs of the 0 value generation circuit 604. Reference numeral 603 denotes a round carry generation circuit for rounding to 2 ⁱ digits. 604 is 0 that produces the number 0
It is a value generation circuit. The round carry generation circuit 603 is configured as follows. Here, as in the previous case, IEEE7
Perform closest rounding based on the 54 standard. Where X
It is assumed that _i-2 is a sticky digit of 2 ^i-2 digits or less. At this time, the carry Cr _j-1 by rounding is as shown in (Table 9).

[Table 9] In Table 9, when (X _i−1 , X _i−2 ) = (1, 0), the carry Cr _j−1 becomes X _i as described above. Therefore, if Table 9 is converted to logic, a carry circuit 603 in FIG. 6 is obtained.

As described above, by inputting a carry by rounding as shown in FIG. 6 as an input value from the lower order of the 2-bit Booth recode circuit, a multiplication processing device as shown in FIG. 7 can be realized. In the figure, a partial product generation and addition circuit 20
The 6, binary number conversion circuit 208 and rounding circuit 209 are the same as those in the above-described embodiment. Also, 2 from 701 to 706
The latch is operated by the phase clocks ph1 and ph2. 7
Reference numeral 07 denotes the multiplier recode circuit shown in FIG. 708
Is a carry generation circuit including a selection circuit 602, a carry circuit 603, and a 0 value generation circuit 604 in FIG. With the configuration as shown in FIG. 7, it is not necessary to pass through the rounding circuit 209 each time during repetitive multiplication, and the signal passes through the rounding circuit 209 only when a final result is obtained. realizable.

As described above, the present invention is applied to the case of using a redundant binary number, the case of using a carry-preserving type numeric value, and the case of using a binary number, for a repetitive multiplication in which a rounding process is performed for each multiplication. Thus, it was described that high-speed repetitive multiplication can be realized. It should be noted that although the case of repeatedly performing multiplication with another high-radix value is not described in this embodiment,
Similar effects can be obtained by using the present invention. Redundancy 2
When generating a binary 2-bit Booth recode circuit, (4)
As shown in the equation, by using B _j instead of the intermediate carry C _j and R _j instead of the intermediate carry S _j , it is also possible to configure a simple logic multiplier recoding circuit. Was.

Next, an embodiment utilizing the present invention will be described below with respect to a repetitive multiplication in which a value obtained by subtracting a multiplier from a certain constant A is multiplied by a multiplicand and the multiplication result is used as an input operand of the next multiplication. First, as the first embodiment, division using the Newton-Raphson method will be described. Now, assume that the division Y / X of the two normalized floating-point mantissas is performed. An algorithm for obtaining an approximate value of 1 / X is the Newton-Raphson method. According to this method, 1 /
The approximate value Ri of X is obtained by a recurrence formula as shown in Expression (15). R ₀ = 1 / X ± δ R _i = R _i-1 × (2-R _i-1 × X) (15) where R ₀ is an initial approximate value of 1 / X, and δ is This is the error between R ₀ and 1 / X. The quotient can be obtained by R _i × Y after the error between R _i and 1 / X is within the desired error. Looking at equation (15), it can be seen that the recurrence equation is a repetitive multiplication by a combination of two type multiplications. The first type is a normal multiplication of α × β, and the second type is a multiplication of α (2-β). In the following, it is stated that the invention is effective for the second type of multiplication.

In equation (15), for simplicity, R _{i-1 is set} to A, and R _i-1 × X is set to B. At this time, equation (15) is a second type of multiplication A (2-B). Here, B is (1
Expression (16) is obtained by using expression (5). B = R _i-1 × X = 1− (X × (± δ)) ^j where j = 2 ⁽ⁱ⁻¹⁾ (16) That is, X is a normalized number (1 = <X <2) Because
It can be seen that B is a value close to 1. Now, suppose that B is represented by a binary number. At this time, in the second type of multiplication A × (2-B), (2-B) becomes (17)
It can be transformed like an equation.

(Equation 7) Equation (17) is modified by taking the two-complement number of the term -B. Here, the LSB is an addition value “1” to the least significant digit of the bit string of B that occurs when taking a two's complement. now,
Assume that B is an 8-digit numerical value for simplicity, and is as shown in Expression (18). B = B ₀ . B ₁ B ₂ B ₃ B ₄ B ₅ B ₆ B ₇ (18) Using equation (18) and expressing equation (17), the following is obtained.

(Equation 8) Therefore, using the present invention, (2-B)
Can be realized as follows. That is, when performing the second type of multiplication A × (2-B), a value (B bar) obtained by logically inverting each digit of B is input to the multiplier recoding circuit, and the second digit higher than the decimal point is placed in the second digit. If “0” is set and “1” is input (LSB) as a carry from the lower end of the recoding circuit that recodes the least significant digit, (2−2)
This is the same as when B) is input as a multiplier.

FIG. 8 shows an example of the above-described operation. A one-value generation circuit 801 generates the LSB in the expression (17). When a signal SUB indicating that the operation is A × (2-B) arrives, the output value of the one-value generation circuit 801 is selected by the selection circuit 602. The selection circuit 802 is input selection means for inputting "0" in the second digit higher than the decimal point when the signal SUB is input, and inputting a logically inverted value of the input value in other cases. Utilizing the present invention, A
When x (2-B) is executed, "0" is set to the second digit higher than the decimal point, and if a logically inverted value is input to the recoding circuit, the subtraction circuit is used as in the related art. There is no need to perform the division at high speed and with a small amount of hardware.

Next, the case where the square root value of X is obtained by using the Newton-Raphson method will be described. At this time, 1 / X
^The recurrence equation for finding ^1/2 is as shown in equation (19). ^{_{R 0 = (1 / X 1/2}} ) ± δ 2 × R i = R i-1 × (3-R i-1 2 × X) ··· (19) wherein, R ₀ is the 1 / X Δ is an error between R ₀ and 1 / X ^1/2 . The square root is _Ri and 1 / X ^1/2
After the error is within the desired error, it can be obtained by R _i × X. In the recurrence formula shown in (19),
R _i-1 ² × X is a numerical value close to 1. Here, R _i-1 ² × X
Is expressed as B, B can be expressed in the same manner as in equation (18).
Here, (19) (3-R i-1 2 × X) in equation R _i-1 ² ×
If X is B, it can be transformed as in equation (20).

(Equation 9) The expression (20) is expressed as follows for each digit.

(Equation 10)

Therefore, using the present invention, the expression shown in (20) can be realized as follows. That is, when the multiplication A × (3-B) is executed, a value (B bar) obtained by inverting each digit lower than the decimal point is input to the multiplier recoding circuit, and “B ₀ ” is input to the first digit higher than the decimal point. And enter " _B0 bar" in the second digit above the decimal point,
If "1" is input (LSB) as a carry from the lower end of the recoding circuit that recodes the least significant digit, it becomes the same as when (3-B) is input as a multiplier. Therefore, (3-
When executing B), a logical inversion circuit is provided for a digit lower than the decimal point, the first digit higher than the decimal point is input as it is, and the logic value of the first digit higher than the decimal point is input for the second digit higher than the decimal point. The inverted values are input, and these output values are input to a multiplier recoding circuit and a carry generation circuit. Then, it is not necessary to use a subtraction circuit as in the related art, and the execution can be performed at high speed with a small amount of hardware.

In the above description, the case where B is a binary number has been described. For further speeding up, the value of the intermediate product (in this case, a redundant binary value) is input as the value of B. At this time, the circuit configuration is as shown in FIG. However, the multiplier recode circuit 2
07, a selection circuit 1201 as input selection means shown in FIGS. 11 and 12 must be added. (15)
When this is shown for the division using the Newton-Raphson method shown in the equation, B shown in the equation (16)
03 and is taken into the selection latch 201.
Then, a simple bit operation is performed before the multiplier is recoded in the next cycle, and a numerical value (2
-B) is recoded. Then, the recode value is input to the partial product generation and addition circuit 206. At this time, the latch 20
The 2 are input R _i-1, multiplied by _{R i-1 × (2-} R
_i-1 × X) is executed. In addition, if this is shown for the square root using the Newton-Raphson method shown in the equation (19), B shown in the equation (20) is output from the latch 203 and is taken into the selection latch 201. Then, in the next cycle, a simple bit operation is performed on the multiplier, and (3-B) is generated using the multiplier recoding circuit 207.
Then, the recode value is input to the partial product generation and addition circuit 206. Further, at this time, the latch 202 are input R _i-1, multiplied by _{R i-1 × (3-} R i-1 2 × X) is executed.

As described above, in the case of division and square root using the Newton-Raphson method, the intermediate product is input to the multiplier recoding circuit, and (2-B) and (3-B) are subjected to simple bit operations during multiplier recoding. Execute by The method of realizing this will be described below.

Now, B is a redundant binary value close to 1 output from the latch 202. For example, the difference between B and 1 is 2 ^-9.
It is assumed that it is less than. A table showing whether or not the value of B (close to 1 and having an error of less than 2 ^-9 ) is present for a total of three digits of the upper two digits and the lower one digit from the decimal point of the redundant binary value is shown below.

[Table 10]

[Table 11]

In Tables 10 and 11, T is −1, and the column of 111 is a value that can be taken by the upper two digits and the lower one digit from the decimal point of the redundant binary value. The column of 112 is 111
Is a column that indicates whether the value of B exists and what the value, if any, is in the sequence of numerical values shown in the column of FIG. The portion indicated by the broken line is a portion that does not exist. Column 113 has a value of 2 for B shown in column 112.
This is a column showing what redundant binary value is obtained when -B is calculated. A column 114 is a column showing what redundant binary value is obtained when 3-B is operated on B shown in 112.

The column 112 is generated as follows.
B is the result of the mantissa multiplication and is always a positive value. The column 111 is a value cut out at the second digit higher than the decimal point. Even if the value is negative, it is only apparently negative. Therefore, for example, TT. In the case of T, since the multiplication result B is always a positive value, the numerical value 1 always exists in the third digit higher than the decimal point. T is 1T. It should be the same value as T (T is -1). 1T. T
Is expressed as 00.1 in binary. That is, if the numerical value 1 continues in the second and lower digits below the decimal point, the numerical value is 1
Will be closer to. The value of B at this time is shown in equation (21). B = 1T. T111111... (21) Implementation of 2-B is as shown in (22-1), which is further modified as shown in (22-2).

[Equation 11]

The realization of 3-B is as shown in (23-1),
This is further modified as shown in (23-2).

(Equation 12)

Tables 10 and 11 are obtained as shown in equations (22-2) and (23-2). Here, attention is paid to the column 2-B (column 113) in Tables 10 and 11. Then
For all 2-B values, the upper three digits are "010", and the value of the second digit lower than the decimal point is less than the decimal point of B if the value of the first digit lower than the decimal point of B is "0". If the value of the first digit lower than the decimal point of B is other than "0", the value of the second digit lower than the decimal point of B remains unchanged. The value below the third digit below the decimal point is B
Is the sign-inverted value of the value of the third lower digit and lower than the decimal point of
Similarly, focusing on the column 3-B (column 114) in FIG. 11, the upper three digits of all 3-B values are “100”, and the value of the lower two digits after the decimal point is: If the value of the first digit lower than the decimal point of B is “0”, it becomes the sign-inverted value of the value of the second digit lower than the decimal point of B, and the value lower than the decimal point of B by 1
If the value of the digit is other than "0", the value of the second digit lower than the decimal point of B remains unchanged. The value of the third or lower digit below the decimal point is a sign-inverted value of the value of the third or lower digit below the decimal point of B. To explain this more specifically, first, A is binary.
When represented by a number, a digit with a weight of 2 ^-i has a non-zero value.
That is, a value whose lower order is 0 from a digit having a weight of 2- ^{(i + 1)} is i
, B is a redundant binary number, Bb is a binary number, and a redundant binary number B
If the value to be close to, 2 ^-m of when viewing Bb 2 binary number
It has a value of non-zero digits with the weights, 2 - with a weight of ^{(m + 1)}
Let m be the value whose lower order is 0 from the digit, and j be the error between B and Bb.
α × 2 ^−j , L is the larger value of i and m, and k is L ≦ k
≤ j-1. That is, k is L or more and j-1 or less
And an exponent of 2. J is a constant B
And the power of 2 shown in the error (α · 2 ^-j ) of Bb
You. Where the multiplier A and the redundant binary value B (converted to binary
A value close to Bb when the
A result similar to the subtraction of B can be obtained. For example, 3
When performing an operation of −B (B is a redundant binary number), A = 11.00000000000 B = 1T. It is assumed that T11111111 (hereinafter T = -1) . Then , assuming that the binary number Bb is B = 0.100000000000 , the error α · 2- ^j between B and Bb is −0.00000.
00001, and j = 9. Also, from A and Bb, i =
0, m = 0. That is, L is the larger of i and m
L = 0. Here, 0 ≦ k ≦ 9-1.
If k is set to 1, the following numerical values are set. Top value → 10 of 2 ^-0 of A-Bb from the host to 2 ^-0. Set 0 from 2 ^-1 to 2 ^-1 → 0 2 ^-2 has a non-zero B value of 2 ^-1 , and 2 ^-2 values of B , ie → 1 2 ^-3 or less sign inversion of B Value → TTTTTTT, that is, the result obtained is 10.01 TTTTTTTT,
This is the same value as (23-2). Did the subtraction like this
You can easily get the same result as the result,
Take as input. That is, it can be seen that the calculations of 2-B and 3-B can be easily realized by the above-described constant setting, simple calculation, and sign inversion.

Actually, FIGS. 11 and 12 are block diagrams of a multiplier recoding circuit having the function of 2-B. 30
1 is a basic unit of the redundant binary 2-bit booth recoding circuit in FIG. The selection circuit 1201 is input selection means for controlling an input value to a basic unit of the redundant binary 2-bit Booth recoding circuit. Table 1 shows the assignment of redundant binary numbers.
It is assumed that it is as shown in FIG. The SUB signal is 2-B
Is executed. When the signal SUB is input, "010" ((Xp, Xm) is added to the upper three digits.
= (00), (10), (00)), and the second digit below the decimal point has a redundant binary input value of the first digit below the decimal point of “0” ((Xp ₋₁ , Xm _{−). 1} ) = (0,0))
, The redundant binary values (Xp _-2 , Xm _-2 ) are swapped and input, and the redundant binary input value of the first digit lower than the decimal point is other than “0” ((Xp ₋₁ , Xm _−1). ) ≠ (0,0)), the redundant binary value (Xp _-2 , Xm _-2 ) is input as it is. Redundant binary values (Xp ₋₁ , Xm ₋₁ ) are swapped in the third and lower digits below the decimal point. It Table 1 Xp _i, that swap Xm _i is to perform sign inversion. Here, the configuration for realizing 2-B has been described. However, even when 3-B is executed, the constant values of the upper three digits are changed from “010” to “10”.
It only needs to be changed to 0 "and can be easily implemented.

As described above, in the multiplier recoding circuit, 2-B and 3-B
In order to execute the above, a selection circuit for a constant and a normal input value is placed in the upper three digits, and a swap circuit for swapping the second digit lower than the decimal point if the first digit lower than the decimal point is "0" is set. A swap circuit may be placed in the lower third digits and below. Therefore, there is no need to use a redundant binary number subtraction circuit as in the prior art, and the processing can be performed at high speed with a small amount of hardware.

Although the above description has been given of the multiplier recode and its selection circuit limited to the forms (2-B) and (3-B), here, a more generalized case, that is, (A-
A case where B) is input to the multiplier recoding circuit will be described. Here, A is a binary constant, and B is an intermediate product represented by a redundant binary number, and is assumed to be in the format shown in equations (24) and (25), respectively. A = A ₀ . A ₁ A ₂ A ₃ ... A _i (24) B = B ₀ . B ₁ B ₂ B ₃ ... B _k (25) Further, the intermediate product B of the redundant binary values is almost equal to a certain constant value Bb represented by a binary number, and the error thereof is represented by a binary number. In this case, it is assumed that the expression is expressed as in Expression (26), and the format of Bb is expressed as in Expression (27). B−Bb = ± α · 2 ^−j where α = 0.1 **, * is 0 or 1 (26) Bb = Bb ₀ . Bb ₁ Bb ₂ Bb ₃ ... Bb _m (27) Here, it is assumed that the relationship of i, m <j <k holds. Using equations (24) to (27), AB is expressed as (2
Equation 8) is obtained. Here, R is the result of subtracting B from A in a redundant binary form. R = AB = (A−Bb) − (± α · 2 ^−j ) (28) When this is represented for each digit, it becomes as shown in (29).

(Equation 13)

[0061] Here, the R as can be seen from (29) 2 ^{- (i + 1)} for the following digit is because from 0 to subtraction of B, the R 2 ^{- (i + 1)} digits is B Equal to the inverted value of Further, (27), (28) from the equation upper digits than 2 ^-m digit R, when converted from 2 ^-m digit higher only to binary, the A-Bb or A-Bb ± 2 ^-m Become. From 2 ^-m upper digit is ^{A-Bb, 2 - (m} + 1) lower digit than digits is equal to the case ± alpha · 2 ^-j converted into a binary number. If the upper part of the 2- ^m digit is A-Bb ± 2 ^-m , the lower digit of the 2- ^{(m + 1)} digit is 2
When converted to a base number, it becomes equal ^to- (± 2 ^-m ) ± α · 2 ^-j . When this state is written by enlarging the value around 2 ^−m , it becomes as shown in (Table 12).

[Table 12]

In Table 12, the digits higher than 2 ^-m digits are equal to or smaller than the subtracted value of the constant A and the constant Bb by 2 ^-m
Only larger or smaller.

Now, consider a case where an error exists below 2 ^{− (m + 1)} . First, it is converted to 0 down to 2- ^{(m + 1)} digits below 2 ^-m digits. In Table 12, A is higher than 2 ^-m digits.
In the case of −Bb + 2 ^−m , the portion of 2 ^−m is propagated to the lower side by a column of T which is continuously lower than 2 ^{− (m + 1)} digits, as shown in Table 1
It looks like 3). Similarly, AB in (Table 12)
The same applies to b-2- ^m as shown in (Table 13).

[Table 13]

Therefore, if there is an error less than 2- ^{(m + 1)} , AB can be realized as follows. In (Table 13), A-Bb is set in the digits higher than 2 ^-m , and 2- ^{(m + 1)}
Set 0 to the digit. 2 - ^{(m + 2)} digit, in (Table 12), 2 - ^{(m + 1)} if the digit is 0 (Table 12) of 2 ^{- (m + 2)} it sets the value of the digit R, If the 2- ^{(m + 1)} digit is other than 0, the value of the ^{2- (m + 2)} digit in (Table 12) is inverted and set. 2
^{For-(m + 3)} digits or less, the value of R may be input as it is. Now, since the value of R of 2 ^−m digits or less is equal to the sign-inverted value of B, the above is rephrased for B.
It looks like this: If there is an error less than 2- ^{(m + 1)} , AB can be realized as follows. In (Table 13), A-Bb is set in the digits higher than 2 ^-m , and 2- ^{(m + 1)}
Set 0 to the digit. 2 - ^{(m + 2)} digit, in (Table ^{12), 2 - (m +} 1) if the digit is 0, 2 B ^{- (m + 2)} the value of the digit sign change set, 2 ^{- If the (m + 1)} digit is other than 0, 2 of B
Set the value of- ^{(m + 2)} digits as it is. For 2- ^{(m + 3)} digits or less, the value of B may be inverted and set.

Although the above description has been made on the case where the error exists below 2 ^{− (m + 1)} , the same can be said generally when the error exists below 2 ^−j digits. Where j ≧ m + 1
It is. In this case, AB can be realized as follows.
A-Bb is set in the higher digits than 2 ^-m , and 0 is set in the 2- ^{(m + 1)} digits to 2 ^-j digits. 2 - ^{(j + 1)} digits, 2 if ^-j digit is 0, B of 2 ^{- (j + 1)} digit value negation Set, 2 ^-j digit of B if it is other than 0 2 Set the value of- ^{(j + 1)} digit as it is. For 2- ^{(j + 2)} digits or less, the sign of the value of B is inverted,
Just set it.

As described above, the general case has been described. When this is applied to the above cases (2-B) and (3-B), the following is obtained. (2-B) → A = 2 Bb = 1 (3-B) → A = 3 Bb = 1 That is, A-Bb is set higher than the decimal point, and “0” is set at the first digit lower than the decimal point. Set and sign-inverted and input the second digit below the decimal point with the value of the first digit below the decimal point of B, and enter the sign of the third and lower digits below the decimal point with the sign inverted after the third digit below the decimal point of B Then come to say.

As described above, in a repetitive multiplication in which a value obtained by subtracting a multiplication result B represented by a redundant binary number from a certain constant A is used as a multiplier of the next multiplication, a redundant binary number adder is conventionally used. It can be seen that there is no need to use it, and it can be realized at high speed with less hardware. In addition,
In the present embodiment, redundant binary numbers have been described. However, the present invention is also effective in the case of a number body in another format with simple logic.

[0068]

According to the present invention, as is apparent from the above embodiment, the carry from the sub-set of the multiplier recoding circuit is as follows.
Selecting and inputting a numerical value according to the carry format has the following effects. (1) In iterative multiplication in which a rounding process of a multiplication result is performed for each multiplication, a binary conversion circuit and a rounding circuit need not be used for each multiplication, and iterative multiplication can be performed at high speed with less hardware and less power consumption. Can be executed. (2) In a repetitive multiplication in which a value obtained by subtracting a multiplier from a certain constant A and a multiplicand and a multiplication result is a multiplier of the next multiplication, it is not necessary to use a subtraction circuit for subtracting the multiplier from the constant A for each multiplication. The multiplication can be performed at high speed with a small amount of hardware and with low power consumption.

In the above (2), when the intermediate product of the previous multiplication is input as the multiplier of the next multiplication, it is necessary to use a subtraction circuit for subtracting the multiplier (intermediate product) from the constant A for each multiplication. It is possible to execute repetitive multiplication at high speed with less hardware and less power consumption.

When the basic unit of the redundant binary 2-bit Booth recoding circuit is constructed, the intermediate sum S _{i is} obtained by using the signal Q _i indicating that the upper digit of the set divided into two digits is 1. , The intermediate carry C _i to the second intermediate sum R
_i and the second intermediate carry B _i, and a logic design is performed, so that a redundant binary 2-bit Booth recode circuit with a small number of transistors and low power consumption can be configured.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiplier recoding circuit and a carry generation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of an iterative multiplication device that repeats with a redundant binary number when the present invention is used.

FIG. 3 is a logic diagram of a redundant binary 2-bit Booth recode circuit and a carry generation circuit according to an embodiment of the present invention.

FIG. 4 is a truth table of a basic unit 301 of the redundant binary 2-bit Booth recode circuit shown in FIG. 3;

FIG. 5 is a truth table of the round carry generation circuit 303 shown in FIG. 3;

FIG. 6 is a logic diagram of a binary 2-bit Booth recode circuit and a carry generation circuit according to an embodiment of the present invention.

FIG. 7 is a block diagram of an iterative multiplication processor that repeats in a binary number when the present invention is used.

FIG. 8 is a diagram illustrating a binary 2-bit Booth recode circuit and a carry generation circuit that subtract a multiplication result from a numerical value 2 and recode the result, according to one embodiment of the present invention.

FIG. 9 is a block diagram of a conventional iterative multiplication processing device that performs a rounding process for each multiplication.

FIG. 10 is a block diagram of a conventional iterative multiplication processing apparatus that multiplies a value obtained by subtracting a multiplier from a certain constant A and a multiplicand, and uses the multiplication result as a multiplier of the next multiplication.

FIG. 11 shows an example of subtracting an intermediate product represented by a redundant binary value from a numerical value 2 according to an embodiment of the present invention, and recoding the result.
A 2-bit booth recode circuit and a selection circuit (part 1).

FIG. 12 shows an example of subtracting an intermediate product represented by a redundant binary value from a numerical value 2 according to an embodiment of the present invention, and recoding the result.
A binary 2-bit Booth recode circuit and a selection circuit (No. 2).

FIG. 13 is a block diagram of a conventional iterative multiplication processing apparatus for multiplying a multiplicand by a value obtained by subtracting an intermediate product (redundant binary number) obtained by a previous multiplication from a certain constant A;

[Explanation of symbols]

101 Basic Unit of Multiplier Recode Circuit 102 Intermediate Sum Intermediate Carry Generation Circuit 103 Recode Value Generation Circuit 104 Selection Circuit 105 0 Value Generation Circuit 106 Round Carry Generation Circuit 201-205 Latch 206 Partial Product Generation Addition Circuit 207 FIG. 1 or FIG. Multiplier recoding circuit described 208 Binary number conversion circuit 209 Rounding circuit 301 Basic unit of redundant binary 2 bit booth recoding circuit 302 Selection circuit 303 Rounding carry generation circuit 304 0 value generation circuit 601 Basic of 2 bit booth recoding circuit Unit 602 Selection circuit 603 Rounding carry generation circuit 604 0 value generation circuit 701 to 706 Latch 707 Multiplier recode circuit 708 Carry generation circuit 801 1 value generation circuit 802 Selection circuit 1201 Selection circuit

Continuation of the front page (56) References JP-A-63-71728 (JP, A) JP-A-63-201825 (JP, A) JP-A 1-255032 (JP, A) JP-A-2-25924 (JP) JP-A-2-51732 (JP, A) JP-A-2-146621 (JP, A) JP-A-2-245824 (JP, A)

Claims (9)

(57) [Claims] 1. An M-digit numerical value of a radix Υ is divided into an N-digit continuous set (M> = N), the set is input, and the numerical value Zg _i of the set is intermediately summed with an intermediate carry S _i. A recoding circuit comprising: a plurality of intermediate sum intermediate carry generating means for dividing into C _i; a recode value generating means for adding the intermediate sum S _i and an intermediate carry C _i-1 from a set lower by one; A selection circuit for selecting one of a plurality of numerical values in the same format as the carry C _i and inputting the selected value as an intermediate carry C _i-1 from one subset of the recoded value generating means; A multiplication processing device comprising: a partial product generation and addition circuit that generates and adds a partial product with a multiplicand based on a recode value output from the recode value generation unit and outputs the product to the recode circuit. 2. A method according to claim 1, further comprising a round carry generating circuit for rounding an output of said partial product generating and adding circuit to a predetermined bit, wherein a carry output of said round carry generating circuit is an input of said selecting circuit. The multiplication processing device according to claim 1. 3. The input data is logically inverted and input to each of said intermediate sum and intermediate carry generating means, and a numerical value "
The multiplication processing device according to claim 1, wherein 1 "is input. 4. The apparatus according to claim 1, wherein an input of said intermediate sum intermediate carry generating means is a signed digit number.
The multiplication processing device according to the above. 5. The multiplication processing device according to claim 1, wherein an input of said intermediate sum intermediate carry generating means is a carry-preserving numerical value. 6. The intermediate sum intermediate carry generating means includes a radix
Divide a signed number of 2 into a continuous set of 2 digits
And a signal Q indicating that the upper digit of the set is 1_iAnd one below
Signal Q from the rank set_i-1And the set value Zg_iTo Z
g_i= 4 x C_i+ S_i, The intermediate sum S_i, Intermediate carry
C_iAnd further divided into R_i= S_i+ Q _i-1, B_i= C_i
+ Q_iThe second intermediate sum R according to the bar_i, The second intermediate carry
B_iThe recoded value generating means generates the second intermediate sum R_iAnd one below
The second intermediate carry B from the order set_i-1And Z_i=
C_i-1+ S_i= B_i-1+ R_i-1 and the recoded value Z
_i2. The method according to claim 1, wherein
Multiplication processor. 7. A digit having a weight of 2- ⁱ having a non-zero value,
From a constant A expressed by a binary number whose lower order is 0 from a digit having a weight of 2- ^{(i + 1)} , a certain numerical value B expressed by a redundant binary number (however, when the numerical value B is converted into a binary number, Bb ± is equal to α · 2 ^-m , where Bb is a non-zero value for the digit with a weight of 2 ^-m
And the lower order is 0 from the digit having the weight of 2- ^{(m + 1)}
number. 1 ≦ α <2, i, subtracts the number consisting m <j) recode
In the multiplication processing device input to the circuit , if L is the larger value of i and m , 2
Until ^-L digit to set the value of the upper from 2 ^-L of A-Bb, 2
Set the numerical value 0 from the- ^{(L + 1)} digit to the 2- ^(k) digit ( L ≦ k
≦ j-l), 2 - (k + 1) in the digit, 2 of a numerical B - 2 ^(k) numeric If non-numeric value of digit 0 B - ^{(k + 1)} digits value,
If a numerical value 0 sets the sign-inverted value, 2 - ^{(k + 2)} to the digit following all the digits, 2 of a numerical B - Set ^{(k + 2)} th digit following the sign inversion value A multiplication processing device , comprising: input selection means for inputting to a recoding circuit . 8. The multiplication processing apparatus according to claim 7, wherein said numerical value B is a carry-preserving numerical value. 9. The input selection means according to claim 1, wherein said lower limit is one lower than a decimal point.
Select the constant value that is in the numerical value above the digit, select the sign-inverted value of the numerical value in the third digit below the decimal point of the input value, and if the value of the input value in the first digit lower than the decimal point is other than the numerical value 0 8. The multiplication processing apparatus according to claim 7, wherein an input value of the second digit lower than the decimal point is selected, and if the numerical value is 0, a sign-inverted value of the input value is selected.