SU991419A2 - Digital function converter - Google Patents

Description

The invention relates to digital computing and can be used for hardware implementation of computing functions.

On the main eute. St. No. 744590 is known for a digital function converter comprising four totalizers, subtractors, two registers, an analysis unit and a control unit, the outputs of the analysis unit are connected to the first control inputs of the first to fourth totalizer subtractors and to the input of the control unit, the first output of which is connected to the control register inputs, and the second output - with the second control inputs of the adders-subtractors, the output of the first register is connected to the first inputs of the first and second adders-subtractors, the second inputs of which Connected to the input of the first register and the first input of the digital functional converter, the output of the second register is connected to the first inputs of the third and fourth adders-subtractors, the second inputs of which are connected to the input of the second register and the second input of the digital functional converter, the outputs of the first and third totalizers of the readers, respectively, are connected to the first and the second inputs of the analysis block.

c This digital function converter is designed to calculate the three functions 2 x / (x + y), 2 x / (x + y) and 2yV (x + y) .2.

A disadvantage of the known converter is the limited functionality.

The purpose of the invention is the extension of the Class of tasks to be solved due to the additional calculation of Functions (xyY / CX + Y). (Shu-x) / (x + y) and (Shu-y} 7 / TX-B).

The goal is achieved by introducing three totalizers into the digital functional converter, the first control inputs of which are connected to the first output of the analysis unit, the second control inputs of the totalizer subtractors are connected to the second output of the control unit, the first information inputs of the fifth

25th and seventh adders-subtractors

connected to the output of the second regibtra, the first and second information inputs of the sixth adder-subtractor and the second information inputs of the fifth and seventh

30th adders-subtractors are connected

with the output of the first register, the third information input of the fifth totalizer is connected to the start input of the converter, the third information inputs of the sixth and seventh totalizer-subtractors are connected to the first input of the converter.

The drawing shows a block diagram of the Converter.

The converter contains adders - calculator 1-7, registers 8 and 9, analysis block 10, control block 11, converter inputs 12-14, and converter outputs 15-21.

Adders-subtractors 5-7 can be executed either in the form of a multi-bit parallel combinational logic circuit (matrix) for adding subtraction, or in the form of a sequential circuit containing one-bit adders-subtractors and a register. The control input of the one-bit adder a-subtractor is the first control input of the adder. The shift register input is the third control input. The input 1L of the first one-bit totalizer-subtractor are the first and second information inputs. The information input of the register is the third input, and the output of the register is the output of the adder-subtractor.

The control unit 11 contains a pulse generator, two triggers, a counter, a decoder, five AND elements, three OR elements and two delay elements, with the first input of the control unit connected to the first input of the first OR element, the input of the first delay element and the first input of the second element OR, the output of which is connected to the first input of the first trigger, the direct and inverse outputs of which are connected to the first inputs of the first and second elements AND, the second inputs of which are connected to the output of the pulse generator, the start and stop inputs of first connected to the output of the first delay element and the second input of the control unit, respectively, the second input of the first trigger is connected to the output of the decoder, the third output of the control unit and the first inputs of the third and fourth And elements, the second inputs of which are connected to the third input of the control unit, the first output of which The output of the third element OR, the first input of which is connected to the output of the fifth element AND, the first input of which is connected to the direct output of the second trigger, whose inputs are connected to the outputs of the even the right element And the first element OR, the second input of which is connected to the output of the third element And, the output of the first element And is connected to the second input

the third OR element, the second input of the control unit and the counter input, the output of which is connected to the input of the decoder, the output of the second element AND is connected to the second input of the fifth element AND through the second delay element to the second input of the second OR element, the output of the first trigger is the fourth output of the block management

The calculations of functions in this converter are based on the simultaneous solution of a system of difference recurrence relations in an iterative process, ..

lo vn

x., h.s.xg x v vj - j-cyj a-% -.

Oh

-)

-JM-Zj- .- 2 „

Io - X

0

about- . U, Vo-0 Nj4r- r4j 2: V v, -:

l (

% X n (/ j. ,,. JX2:

; Xil-v

about qj ,,,

where 3 O, n is the iteration number,

i Oh, p - weight or indicator

iterations /

n is the number of bits of the operand (one of argumpnt).

The recurrent relations of the algorithm have recurrent properties and are calculated simultaneously in a single iterative process. Each relation can be calculated either in parallel in one clock cycle or sequentially in n + m clock cycles, where m Hlog is the number of additional bits of registers and accumulator chimeters to compensate for the truncation error of numbers during their shift. The ratio x- is realized in the subtractor-subtractor 1, the ratio is y. is implemented in adder-subtractor 3, the ratio ZJ is realized in adder-subtractor 2, the relation Uj is realized in adder-subtractor 4, the ratio V; is implemented in adder-subtractor 5, the ratio W: is realized in adder-subtractor b, the ratio Q.I is realized in. summator V. The values of y2g are obtained respectively in registers 8 and 9. The logical equation y - x. resolved in analysis block 10. The calculations in the converter are carried out as follows.

The initial value of the x code is set in the register viv of the subtractors 1-2 and 6-7, and the value of the y code is set in the register 9 and in the adders-subtractor 3-4 On the starting pulse from the input 14 a zero value is set in the adder-subtractor 5.

At the moment — the occurrence of the end of the iteration in the control unit of the pulse in the analysis block 10 — the value of the digit q is generated for the following iteration. With values of a. - "- 1 in adders -. subtractors 1.4, b, addition is performed on the first and second inputs of adders-subtractors 5 and 7, and in subtractors-2-3, on the second input of adder-subtractor 5 and on the first input of adder-subtractor 7, subtraction. When q; / -1 their operation mode is reversed.

If the contents of x and y are equal: in subtractors 1 and 3, J in block 10 of the analysis, a signal is generated at the second output, according to which in block 11 of control, the clock generator x is turned off and the calculation process is completed. In this case, adders x 1 and 3 (outputs 15 and 17) contain the value of the function 2 xu (x + y), adder subtractor 2 (output 16) contains the value of the function 2xV (x + y), and adder 4 (17 output 18) contains the value of the function (x - "- y), subtractor 5 (output 19) contains the value of the function (xy) / (x + y), and summing pad b (output 20) 5. contains the value of the function (Shx-x) / (x - “- y), in the adder-subtractor 7 (output 21) contains the value of the function (Shu-y) / (x - | - y).

The maximum computation time of the six specified functions in this converter for the parallel principle of operation in clock cycles is equal to, and for the sequential principle of operation in cycles, it is equal to

TK, (n + t + 1). .

However, due to the asynchronous mode of operation (interruption of the computation process with x yi) for most of the arithmetic values, the computation time is significantly less than the maximum value, since the process ends in an iteration whose number is less than the value n.

In the case of error, the computation error is. of these functions is determined

0, the length of the bit grid of registers and adders and when using additional bits m are always less than one of the last least significant bit n.

five

Claims (1)

Invention Formula Digital functional converter on author St. 744590, differing from the fact that, in order to expand the class of problems to be solved, by additionally calculating the functions (xy) / (xy), (Zhu-x / 5 / (x + y) and (Zhu-y) / (), three adders-subtractors are entered into it, the first control inputs of which are connected to the first output of the analysis unit, the second control inputs of the adders-subtractors are connected to the second output of the control unit, the first information inputs of the fifth and seventh totalizers-subtractors are connected to the output of the second register, the first and second informational inputs of the sixth 5 totalizer subtractors and the second information inputs of ptgr and the seventh adders-subtractors are connected to the output of the first register, the third information input of the fifth adder0 subtractor is connected to the start input of the converter, the third information inputs of the sixth and seventh totalizers-subtractors are connected to the first input of the converter. five Sources of information taken into account in the examination 1, USSR inventor's certificate 744590, class, G About F 7/38, 1978 (prototype),