SU732861A1 - Device for computing inverse value - Google Patents

Description

The invention relates to computing and can be used in digital computers and devices. Devices for calculating the reciprocal, based on universal digital computers l, 2 and 3, are known. The return value in such devices is computed using software methods. However, such a calculation of specialized computing devices is irrational, since it is associated with large hardware costs and, moreover, requires a considerable amount of time, since multiple memory calls are necessary. The closest to the proposed device is for calculating the inverse value, which includes input and output registers (adders), an initial approximation selection unit, a duplicating unit, a digital comparator, a forward and reverse code switch, a fixing unit of a given approximation accuracy. and the control unit of the correct bits in the next approximation of the reciprocal. The calculation of the inverse value in this device is done by. iterative formula. - It highlights the initial approximation and performs a certain number of iterations, which depends on the required accuracy of the calculations. However, such a device has a low speed when working in real-time process control. The purpose of the invention is to increase the speed of interaction. This goal is achieved by the fact that the device for calculating the reciprocal, which includes two adders, contains a third adder, a register, a block of OR elements and a bit analysis block, with the outputs of the first and second adders connected to the first in the second groups of inputs of the block of OR elements corresponding to the CTRT elements; the outputs of the block are connected to the inputs of the third adder, the outputs of the register are connected to the information inputs of the first and second combinators, the first and second control inputs of which are connected to the first and second the information inputs of the device, respectively, and the third and fourth control inputs to the first and second outputs of the device, respectively, the first control input of the device is connected to the control input of the bit analysis unit, the outputs of which are connected to the outputs of the device, and the sign and information inputs - to the sign and information outputs of the third adder, respectively; the second control input of the device is connected to the control inputs of the register and the third adder; In addition, to achieve the set whether the bit analysis block contains the AND, OR, AND-NOT and prohibition elements, and the information inputs of the bit analysis block are connected to the inputs of the OR element and the AND-NOT element, the outputs of which are connected to the first inputs of the prohibition elements and AND, respectively, the second the inputs of which are connected to the control input of the bit analysis unit, the sign input of which is connected to the control input of the prohibition element and the third input of the And element, the outputs of which are connected respectively to the first and second outputs of the bit analysis unit. The drawing shows a functional diagram of the device, the Device contains a register 1, adders 2 and 3, a block of 4 elements OR, an adder 5, a block 6 of analysis of bits. The outputs of register 1 are connected to the inputs of adders 2 and 3. Adders 2 and 3 contain h information bits (h is the width of the operand and result representation) and one sign. The outputs of adders 2 and 3 are connected to the inputs of a block of 4 OR elements, and the sign bits are connected to the inputs of the first two elements OR of a block of 4 OR elements, and each i -th data bit of adders 2 and 3 is connected to the input of (i + l) - element OR block 4 elements OR. The outputs of the block 4 of IDN elements are connected to the inputs of the adder 5, containing (1+ 3) bits, one of which is signed, and two are intended for storing the whole part. Block, 6 analysis of soda bits & elements OR 7 1 7, AND-NOT 8, prohibition 9 and element AND 10. The outputs of the four most significant bits of the adder 5, starting with the second, are connected to the inputs of element 7 and element 8, the outputs of KOTopibix The inputs of element 9 and 1O are connected respectively, the first code (digit) bit of adder 5 is connected to the control input of element 9 and to the input of element 10. The device also contains information inputs 11 and 12j, control inputs 13 and 14, and outputs 15 and 16. Information input 11 of the device is connected to the control input of receiving the direct sum code. 2 and with a control input for issuing an additional code of the adder 3. Information input 12 of the device is connected to the control input of receiving an additional code of the adder 2 and to the control input of issuing the direct code cjTviMaTopa 3. The control input 13 of the device is connected to the control input of the unit 6 analysis. bits, which is connected to the inputs of the prohibition element 9 and the element I 1O, the control input 14 of the device is connected to the control inputs of the shift of register 1 and the adder 5. The output 15 of the device is connected to the first output of the block 6 analysis of bits and connected to the output control inputs the additional code of adder 2 and the reception of the direct code of the adder 3, the Output 16 of the device is connected to the second variable of the bit analysis block 6 connected to the control inputs of the issuance of the direct code of the adder 2 and the reception of the additional code of the adder 3. The first and second th analysis unit outputs are connected to outputs and barring element 9 and element 10 respectively. As accumulators 2, 3 and 5, accumulating adders are used. Summation in the bag-actor 5 is performed with a delay. When shifting in the adder 5, the contents of the third bit (the second bit of the whole part) are recorded in the first and second bits of D1s1. Otherwise, the shift is produced as usual. Receiving and issuing an additional code in Mmators 2 and 3 can be performed by receiving (issuing) a return code with adding one to the least significant bit. To present 5 the operand X and the result Y-4, a redundant symmetric binary system with digits, 1,

The device operates according to the following algorithm.

-h

l, if N.-2 0, ecNM-2 N.2

&. Vf 1

one

-2

1 if i

 -YH., 23. .u.

 the next figure of the operand

Where

(t, oi);

the contents of the adder 2 in the i - cycle calculations;

next digit of the result; X - Contents of the adder 3 in the i cycle of calculations; the contents of the adder 5 to 1-1 beginnings of the i-th cycle of computing N; - the contents of the adder 5 in

i th cycle.

Initial state Cr 2 | X -Yo-O Limit value of the argument to 2 (1,

In the initial state, the highest digit in the register 1 is 1, in the remaining bits - zero.

The return value of the source operand is calculated in (H + 3) cycles, each of which consists of three ticks. In the first cycle of each i-th cycle, the next bit of the operand arrives at the inputs of the device (the operand enters, starting from the higher bits). In this case, if a single signal arrives at the information input 11 of the device, this indicates that the next bit of the operand is numerically equal to 1. If the single signal goes to 1 information input 12, the next bit of the operand is numerically equal to T. If the unit bit is not received at any of the inputs 11 and 12, the next bit of the operand is numerically 0. Depending on the signal received at the inputs 11 and 12, the contents of the adder 3 are added or subtracted from the Contents of the adder 5 with a shift by one bit to the left. In addition, the content of the adder 2 is added to the direct or additional content code of register 1. As a result, the value in the adder 5 is formed, and

Zummator 2 - the value of X -. By the beginning of the second cycle, the information signals of the coincides 11 and 12 are removed.

In the second cycle, the control signal received at control input 13 is used to output information to the outputs 15 and 16 of the device. Moreover, if a single signal appears at the output 15, this indicates that

0, the next bit of the result is numerically equal to 1. If a single signal appears at output 16, the next bit of the result is 1. : If a single signal does not appear on any of the outputs 15 and 16, the next bit of the result is numerically equal to 0. For the single signal from output 15 to the i-th bit of adder 3, 1 is added and an additional adder code is issued.

0 2. For a single signal from the output 16 of 1 - its discharge of the adder 3, the unit is subtracted, which is carried out by the reception of an additional code from register 1, and a direct code is also issued

5 adder 2. As a result, a code is formed at the end of the second clock cycle (as summation in the adder 5 is performed with a delay) in the adder 5 in the second clock cycle forms 0 for the code K.

In the third clock cycle, the control signal arriving at the device control input 14 is shifted left by one bit.

5, adder 5 and right shift by one bit of the contents of register 1. This completes the cycle of computing.

As a result of performing (AND + 3) cycles on inputs 15 and 16 of the device, a discharge for a number of times (starting from the highest bits) is formed, the value of the reciprocal of the original operation, the rand delayed by three bits, t .

function Y-, represented by h.

Accurate binary code with numbers 1.0, 1,

in every category de. As a result of (P + 3) cycles, the result is symmetrically rounded.

Claims (4)

By combining in time the process of one-bit input of the operand and calculating the next digits of the result of its discharge, which carry a large format of HeMj are calculated in the first cycles. lah. This allows efficient use of the device in process control systems in real time when the process of forming the numbers of the operand is limited by external factors, and the control action for the executive body of the system is formed directly from the results of the calculations. In addition to | performance increases when working in a computing environment where devices of this type are connected in series. Bitwise input of the operand and the result of the result allows a long-term reduction in the number of external links, which does not depend on increasing the size of the operand. This determines the possibility of implementing the device in the form of a large integrated circuit. Claim 1. Device for calculating the inverse value, containing two adders, characterized in that, in order to improve speed, the device contains a third adder, a register, an OR element block and a bit analysis block, the outputs of the first and second adders are connected to the first and the second group of inputs of the block of elements OR coTBeTCTBeHHOj, the outputs of the block of elements OR are connected to the inputs of the third adder, the outputs of the register are connected to the information inputs of the first and second adders, the first and second control inputs Which connects to the first and second information inputs of the device, respectively, and the third and fourth control inputs to the first and second outputs of the device, respectively, the first control input of the device connected to the control input of the bit analysis unit, the outputs of which are connected to the outputs of the device , and the sign and information inputs are connected to the sign and information outputs of the third adder, respectively, the second control input of the device is connected to the control inputs of the register and the third adder. 2, The device according to claim 1, wherein the bit analysis block contains AND, OR, NAND and inhibit elements, and the information inputs of the bit analysis block are connected to the inputs of the OR element and the NAND element, the outputs of which are connected to the first inputs of the inhibit and And, respectively, the second inputs of which are connected to the control input of the bit analysis unit, the sign input of which is connected to the control input of the inhibit element and the third input of the And element, whose outputs are connected respectively to the first and second outputs of the block analysis of bits Sources of information taken into account during the examination 1. Accepted for UK No. 13О40О8, cl. G 4 A, 1973. 2. US patent N 374O722, cl. 34O-172.5, 1973. 3.Patent of France No. 2147937, cl. Q 06 F, 1973. 4. The author's svir; the letter of the USSR № 362296, cl. G 06 F 7/39, 1969.