SU1176322A1 - Computing device - Google Patents

Abstract

. 1. COMPUTER DEVICE containing two registers, a normalization unit, a summation determination unit, a control unit, a switching unit and a half adder, the sum output of which is connected to the first input of the control unit and the first information input of the first register, the second information input of which is connected to the first output of the block switching, the second output of which is connected to the information input of the second register, the output of which is connected to the input of the first term of the half adder, the input of the second term of which is connected En with the output of the first register and with the first input of the normalization unit, the output of which is connected to the control input of the first register, and the second input - with the control input of the mode setting in the gold 1-code of the device and the first control input of the switching unit, The first information input of which is connected to the output of half-adder transfers, the input of the block for determining the end of the summation and the second input of the control unit, the control input for setting the operating mode in the binary system of the connection It is provided with a second control input of a co-switching unit, characterized in that, in order to expand its functionality by performing an additional arithmetic shift operation of the number represented in the golden J-code, the trigger, the delay element and the intermediate results correction unit are introduced into it. The information input of which is connected to the output of the first register and the second information input of the switching unit, the third control input of which is connected to the control input (the direction code and The device shift and control inputs are the home of the intermediate correction block, the output of which is connected to the third information input of the switching unit, the fourth control input of which is connected to the trigger output directly and the input of the delay element whose output is connected to one trigger reset input, The clock 09 input is connected to the control of the IS9 IS8 for the device shift enable input, the information input of which is connected to the single potential bus, and the inverse output to the fifth control input of the block Switching ka. 2. The device according to claim 1, characterized in that the switching unit comprises a switch, three groups of AND elements, two groups of OR elements, an AND element, the first output of the switching unit being connected to the outputs of the OR elements of the first group, the first inputs of which are connected to the switch output and the second entrances

Description

with the corresponding outputs of the elements of the first group and the first inputs of the elements OR of the second group, the outputs of which are connected to the second output of the switching unit, the first information input of which is connected to the first inputs of the elements of the first and second groups, the second inputs are connected to the fifth control input of the block switching, the first control input of which is connected to the third and first inputs of the elements of the first and third groups, respectively, the second inputs of the elements of the third group are connected to the third information input of the block switching, the second control input of which is connected to the third inputs of the elements of the second group and the first input of the element I, the second input of which is connected to the second information input of the switching unit and the third inputs of the elements of the third group, the fourth inputs of which are connected to the first control input the switch and the fourth control input of the switching unit, the third control input of which is connected to the second control input of the switch, whose information inputs are connected to the second information input switching unit and with the output element And the outputs of the elements And the second and third groups are connected to the second and third inputs of the corresponding elements OR of the second group.

The invention relates to computing technology, is intended for performing operations of addition - subtraction and arithmetic shift of multi-bit parallel codes and can be used in specialized processors with high reliability of information processing. The aim of the invention is to improve the functionality of the device by performing the additional arithmetic shift operation of the number represented in the gold I-code calculus system. In the gold 1-code system, the negative number A is represented by an additional code of the form 1-1A (. Then, after shifting to / offsets, it should be (1- | A |; When performing the usual unmodified shift A.ddd by k times - Row to the right, we get A, (i-iA). The value differs from / -k 1 the required value (A-оС value X, l- / A ((iJ-fltJ + jAI-dL: "1-rfl Investigator; But to get the correct result, add the value of Xi to the code obtained after shifting the bits to the right. When performing the shift of the additional code by the bits to the left, m. The value differs from the required value (, by the value of .V and 2-mi ;-(,. |, c1, | 4-h.: ° C. M-s. - Therefore, to get the correct result, the code obtained after the shift the bits to the left must be corrected by the value of x. Figure 1 shows the computing device, Fig. 2 shows the switching unit circuit. The computing device (Fig. if contains the control inputs 1 and 2 of the mode setting in the gold I-code the system and the binary system of the device, the first 3 and second 4 registers, block 5 normalization, half-adder 6, block 7 to 1D1I, control unit 8, summation end determination unit 9, intermediate result correction unit 10, trigger 1I, delay element 12, control input 13 of directional code and device shift constant, control device 14 for resolution of device shift.

Switching unit 7 {FIG. 2 contains switch 15, element AND 16, three groups of elements AND 17-19, two groups of elements OR 20 and 21.

Register 3 is designed to hold the shift and add operand, as well as subtotals. Register 4 is intended for the storage of the addition operation and intermediate transfers. Block 5 normalization is designed to bring the code in register 3 to normal form, i.e. the absence of two rows of units in the code, and has a size equal to the size of the register 3 minus. In the i-th bit of block 5, the function F is set to the unit i-ro bit of the register 3

fM 3ia, -. ia -: 2Va as-) b., 1 v va, .. b, 1.

01 10

11 01

01

ten

ten

ten

eleven

eleven

eleven

eleven

eleven

where a- is the value of the f-ro bit of register 3,

Block 9 of determining the end of summation is designed to determine the moment of the end of the addition of subtotals with intermediate transfers based on the zero value of intermediate transfers and implements the function

 to; Trigger II and pre delay element 12; {; are assigned to form a control shift pulse of a desired duration. The intermediate results correction unit 10 is designed to store and issue corrective terms used to obtain the correct result of the shift of the additional gold T-codes.

The direction of the shift is encoded as follows: O is the shift to the right, 1 t is the shift to the left, the constant of shift (the binary number system.

The type of the correction term depending on the input signals of the block IO is presented in the table (for Jc 3).

0.01

0.1

0.100

1.01

0.01

0.00

1.01

0.00

1.01

1.01

0.00

0.00

about . 01 The device works as follows. When working with numbers represented by gold 1-codes, the potential is established on control bus 1. Trigger 11 is in the zero state, on its inverse output. de 17 - a single signal. Block 7 of the mutation is configured in such a way that the transfer output of the half-adder 6 is connected through the group of elements I 18 and the group of elements AHM 2 with a shift of 2 bits to the right to the input of the register 4 and through the group of elements SHSh 20 with a shift of 1 bit to the left - to the input of register 3. The same bits of the gold 1-codes are added according to the following rules: 0 + 0 0 0 + 1 1 1 + 1 1001 Since the gold 1-codes of the terms are presented in normal form, the transfer index from the i-ro output p The renals of the half-adder 6 can immediately be placed in the (1 + 1) -th bit. register 3 and the (-2) th register bit of register 4. Register 3 also records the code of the initial amount from the output of the sum of half adder. Then the code in register 3 is brought to normal form using block 5 of normalization. The addition of intermediate sums with intermediate transfers continues until all intermediate transfers become equal to O, which is determined by block 9. The process of adding gold 1-codes is controlled by block 8.. If it is necessary to perform an arithmetic shift operation on the code in register 3, control pulse 14 receives a shift pulse, and input 13 contains the shift direction code and the shift constant code V. Trigger 11 goes to the unit state. If in register 3 there is an extra gold one. J-code, the output of the correction unit 10 through the group of elements AND 17 and the group of elements OR 21 commutes with the input of register 4, where the correction term is written. The signal from the direct output of the trigger 11 opens, the switch 5 and the content of the re- is shifted. the horn 3 by the value defined by the code on Input 13. The signal from the output of the AND 16 element enters the higher | that are released after the shift to the right (register bits 3, When shifting, additional gold1; about the t-code, the unmodified shift is performed, i.e. registers 3 are written with zeros in the high bits, and when a normal binary code is shifted, there is an mdigit shift.At a time interval sufficient to shift the contents of the register 3 and write the correction term in register 4, the signal from the output of trigger I1 passes through the delay element R- input tr and the last one is nullified. Next, the contents of register 3 are added to the correction term in register 4, described in the above manner. When operating in the binary classical number system, a signal is sent to the control bus 2, the transfer output of the half adder is connected to the input register 4 is shifted by bit to the left; block 5 is normalized; the output of block 10 is blocked;

1 13

.one

Claims (2)

. I. A COMPUTER DEVICE containing two registers, a normalization unit, a summation determination unit, a control unit, a switching unit and a half adder, the sum output of which is connected to the first input of the control unit and the first information input of the first register, the second information input of which is connected to the first output of the unit switching, the second output of which is connected to the information input of the second register, the output of which is connected to the input of the first term of the half-adder, the input of the second term of which is connected to the output the first register input and with the first input of the normalization block, the output of which is connected to the control input of the first register, and the second input - with the control input of setting the operating mode in the golden 1-code number system of the device and the first control input of the switching unit, the first information input of which is connected to the half-admitter carryover output, the input of the end of the summation determination unit and the second input of the control unit, the control input of setting the operating mode in the binary number system of the device is connected to the second control with the input of the switching unit, characterized in that, in order to expand the functionality by performing an additional arithmetic shift of the number represented by a 1-code number system by scrolling, a trigger, a delay element, and an intermediate result correction block, an information input are introduced into it which is connected to the output of the first register and the second information input of the switching unit, the third control input of which is connected to the control input of the direction code and the device shift constant and the control input of the intermediate results correction unit, the output of which is connected to the third information input 'of the switching unit, the fourth control input of which is connected to the direct output of the trigger and the input of the delay element, the output of which is connected to the trigger reset input, the clock input of which is connected to the control input of the shift resolution device, the information input of which is connected to the unit potential bus, and the inverse output is connected to the fifth control input of the switching unit. 2. The device according to π. 1, characterized in that the switching unit comprises a switch, three groups of AND elements, two groups of OR elements, an AND element, the first output of the switching unit being connected to> the outputs of the OR elements of the first group, the first inputs of which are connected to the output of the switch, and the second inputs 1 176322 with the corresponding outputs of the And elements of the first group and the first inputs of the OR elements of the second group, the outputs of which are connected to the second output of the switching unit, the first information input of which is connected to the first the inputs of the elements And the first and second groups, the second inputs of which are connected to the fifth control input of the switching unit, the first control input of which is connected to the third and first inputs of the elements And the first and tr According to the group of groups, the second inputs of the AND elements of the third group are connected to the third information input of the switching unit, the second control input of which is connected to the third inputs of the AND elements of the second group and the first input of the AND element, the second input of which is connected to the second information input of the switching unit and third inputs of the elements And the third group, the fourth inputs of which are connected to the first control input of the switch and the fourth control input of the switching unit, the third control input of which is connected to the second control input of the switch, the information inputs of which are connected to the second information input of the switching unit th with the output of the AND element, the outputs of the And elements of the second and third groups are connected to the second and third inputs of the corresponding OR elements of the second group.