SU888204A1 - Storage - Google Patents

Description

(5) STORAGE DEVICE

The invention can be advantageously used for storing and processing requests for interruption of computing systems with a large number of request sources. Known storage devices 1, 2. One of the known memories contains memory registers, information from which is read by a common resolution signal, while the information stored on the register is simultaneously received on the output buses. Moreover, if it becomes necessary to analyze the state of only one or several bits, it is necessary to use an arithmetic-logic device and do this with the help of the operations of logical multiplication, logical addition, comparison, and conditional transitions G1. The disadvantage of this memory is limited scope. Of the known devices, the closest technical solution to the invention is a memory device containing two groups of I circuits, the outputs of which are connected to the outputs of the charger, two registers whose outputs are connected to the corresponding first inputs of the two groups of AND circuits, and the second inputs of the first group of AND circuits respectively, with the first group of memory inputs f2j. The disadvantage of this memory is that it does not allow selective reading of information from registers for individual bits, as well as the fact that in it, based on the principle of its operation, more than two registers cannot be applied. This limits the scope. The aim of the invention is to expand the field of application of the memory device by providing the possibility of selectively reading information on the registers and discharges of the device.

The goal is achieved by the fact that in a memory containing groups of main elements AND whose outputs are memory outputs, main registers whose outputs are connected to the first inputs of main elements AND groups, the second inputs of main elements and one of the groups are respectively the main memory inputs , groups of elements OR-NOT are introduced, additional registers and groups of additional elements AND, Outputs of additional elements AND groups are connected to the corresponding memory outputs, outputs of additional registers are connected to the first input am additional elements and groups, the second inputs of which are connected to the outputs of respective OR-NO elements of groups, the first inputs of which are respectively connected to the inputs of the main memory, the second inputs of OR-NO elements of each group are combined to additional inputs ZU.I

The drawing shows a functional diagram of the proposed memory.

The drawing indicates the main

1.1-1.P memory.

The memory contains the main registers А.1 and, 2, additional registers 5, groups 6.1, 6.2 and 7, respectively, the main 8.1 and additional 8.2 elements AND group 9 elements ILINE 10.

The outputs of the main elements AND 8.1 of groups 6.1 and 6.2 are outputs 3 of the memory. The outputs of the main registers k.} And .2 are connected to the first inputs of the main elements AND 8.1 groups 6.1 and

6.2 accordingly. The second inputs of the main elements AND 8.1 of one of the groups 6.1 are respectively the main inputs 1 of the memory. Dog outputs (additional elements AND 8.2 of groups 7 are connected to corresponding outputs 3 of memory. The outputs of additional registers 5 are connected to the first inputs of additional elements AND 8.2 of groups 7, the second inputs of which are connected to the outputs of the corresponding elements OR NOT 10 groups 9 whose first inputs are connected respectively to the main inputs 1 of the memory. The second inputs of the elements IDN-NOT 10 of each group 9 are combined and are the additional inputs 2 of the memory.

The memory works in the following way. When single signals are applied to certain main inputs 1, signals corresponding to the contents of the read bits of one of the main registers appear on the corresponding device outputs 3. Thus, selective reading of the contents of the individual bits of the main registers is carried out. 1. When zero signals are applied to the main inputs 1 of the device, the outputs at its outputs 3 appear corresponding to the contents of one of the other main registers k.2 or additional registers 5 whose number is determined by the absence of a signal at the corresponding auxiliary input 2 of the device. Thus, selective and mixed reading of the contents of the main 4.1 and 4.2 and additional 5 registers is carried out, which allows to generate codes with the specified content.

The technical and economic advantage of the proposed storage device consists in a wider, in comparison with the prototype, field of its use, achieved by providing the possibility of selective reading in registers and device delays.

Claims (1)

Invention Formula A storage device containing groups of main elements And whose outputs are device outputs, main registers whose outputs are connected to the first inputs of main elements And groups, the second inputs of main elements And one of the groups are respectively the main outputs of the device, characterized by that, in order to expand the field of application of the device by providing the possibility of selectively reading information on the registers and discharges of the device, it contains groups of elements OR NOT, additional registrations ry and groups of additional elements AND, and the outputs of additional elements AND groups are connected to the corresponding outputs of the device, the outputs of additional registers are connected to the first inputs of additional elements AND groups, the second inputs of which are connected to the outputs of the corresponding elements ORINE groups, the first inputs of which are connected respectively to the main inputs devices, the second entrances ele $ 88820 OR-NOT of each group of unions - 1, I / O channels 3BMEC-t020. pvllyutsya and other entrances - Under General Ed. A.N., Larionova N, mi devices. Statistics, 1976, p. Sources of information, 2, Japan Application No. 5t 1I3lt taken into account in the examination of cl. 97 / C / 7g 979 (prototype).