SU822290A1 - Semiconductor storage - Google Patents

Description

oystva In such a device, the speed of transferring the address code from the processor increases, but the speed of information transfer does not increase, since information from the various marina lines is received through the general information, and its processing speed is determined by the speed of the blocks of the bits. The time of checking a memory device depends on its capacity and on the speed of information processing by the memory device. So, to test a device with a cycle time of 1 MKS, with a capacity of 4096 bits, the jump units and zeros need to be spent on the time determined by the formula

 t 8 4096 1 10 2.24 min where N is the capacity of the device under test, 1 c is the cycle time of the test device

devices.

To test a device with a capacity of 16384 bits with the same speed, it will take 35.84 minutes. The dramatic increase in verification time must be taken into account when developing semiconductor storage devices with high information capacity, since this reduces the performance of the control equipment, increases the cost of control and the cost of the device.

The aim of the invention is pov. information capacity of the device.

The goal is achieved by the fact that in a semiconductor memory device containing a matrix drive, the outputs of which are connected to one of the selector inputs and output buses of the device, one of the inputs of the matrix accumulator is connected via the sampling drivers to the d outputs of the address decoder, the inputs of which are connected to one of the register outputs addresses whose other outputs through the address drivers are connected to the address inputs of the matrix storage device, information buses and read / write buses are entered into it An additional address decoder, OR elements and OR-NOT, with one of the inputs of the additional address decoder connected to the first write-read bus, other inputs to the other selector inputs and the corresponding outputs of the address register, the outputs of the additional address decoder connected to the first inputs of the elements OR, the second inputs of which are connected to the second write-read bus, and the outputs of the SHS elements are connected to other inputs of the matrix storage device, the information inputs of which are connected to the outputs of the corresponding elements Comrade NOR inputs are connected to the input data lines.

The drawing shows a functional diagram of a semiconductor storage device.

The device contains memory blocks integrated into a matrix storage device 5 1, output buses 2, information register 3, selector 4, device output buses 5, inputs 6 and 7 of the matrix storage device, sampling units 8, address decoder 9, address register 10, address drivers 11, address input 12 of matrix storage, additional address decoder 13, elements 14 OR, elements 15, write-read buses 16 and 17, information inputs 18 of matrix 5 storage, input information buses 19 and 20 ..

 The device has two modes of operation: the mode of operation as part of the videoter. minal complex and control mode.

During operation in a video terminal complex, information is recorded as in a one-bit memory. The address code from the outputs 5 of the register 10 of the address is fed to the inputs of the drivers 11, the inputs of the decoder 9 and the decoder 13. Input information is fed through bus 20, the write operation code via bus 16. Sample drivers 8 select the necessary row of memory blocks of the matrix drive 1, the decoder 13 selects the required block in the selected line, which, by the operation code received via bus 16, switches to the write mode, and the remaining blocks of this line remain in the read mode. The information received via bus 20 is recorded in the selected memory block. In the read mode, the information is read simultaneously from all the memory blocks of the selected row and is written to the information register 3., which operates in the information shift mode and converts the parallel code into

5 formations in sequential that

increases the speed of information transfer. There is also the possibility of transmitting one bit of information to the output buses through. selector 4.

In the control mode, the write code enters the bus 17, and the information on the buses 19. The selection of the memory blocks is carried out by the decoder of 9 lines. Information is recorded. simultaneously to all blocks of the selected line. When reading in the control mode, the read information enters the output buses 5 through the information register 3 with a parallel code.

0 In the proposed device, inputs are used to decipher the recording of memory blocks, which makes it possible to increase the capacity of the device not by increasing the number of blocks.

Claims (2)

5 in the column, and by increasing the output of the decoder of the operation code. At the same time, the capacity of the input and output information buses is reduced, which increases the speed of the device. Simultaneous reading of information from all blocks of memory of a selected line and transferring it by a sequential code significantly increase the speed of information processing of the storage devices of the video terminal complex, which has a sequential selection of information. Simultaneous reading and issuing. information from all the memory blocks of the selected line in the control mode allows to reduce the time of its control and reduce the cost of the device. Claims A semiconductor memory device containing a matrix storage device, the output of which is connected to one of the selector inputs and output device buses, one of the inputs of the matrix storage device is connected to the outputs of the address decoder, the inputs of which are connected to one of the address register outputs, the other outputs of which through address shapers are connected to the address inputs of the matrix on the drive, information buses and write-read buses, characterized in that, in order to increase No information capacity of the device, an additional address decoder, elements OR and ILINE are entered into it, and one of the inputs of the additional address decoder is connected to the first write-read bus, the other inputs to other inputs of the selector and the corresponding outputs of the address register, outputs of the additional address decoder connected to the first inputs of the elements OR, the second inputs of which are connected to the second write-read bus, and the outputs of the elements OR are connected to other inputs of the matrix storage device, informational in ode which are connected to respective outputs of OR-NO elements whose inputs are connected to the input data lines. Sources of information taken into account during the examination 1. Vitaliev G.V. and others. Development of semiconductor memory devices. Issues of radio electronics. Ser.Electronna computer technology, 1977, issue 5, fig.12. . 2. USSR author's certificate No. 598120, C. 11 C 11/40, 1975 (prototype). S