KR950009076B1 - Dual port memory and control method - Google Patents

Abstract

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Description

Dual Port Memory and Its Control Methods

1 is a block diagram showing the configuration of a dual port memory according to an embodiment of the present invention.

2 is a timing chart for explaining the serial write operation by the dual port memory of FIG.

FIG. 3 is a timing chart for explaining serial lead mode mode write operation by the dual port memory shown in FIG.

4 is a timing chart for explaining the serial read operation by the dual port memory of FIG.

5 is a block diagram showing the configuration when image processing is performed using a dual port memory according to one embodiment of the present invention.

FIG. 6 is a timing chart for explaining the image processing operation shown in FIG.

7 is a timing chart for explaining the time required for the read mode pie write operation when the dual port memory according to an embodiment of the present invention is used.

8 is a timing chart for explaining the time required for the read mode pie write operation using the page mode by the conventional dual port memory.

Fig. 9 is a block diagram showing a configuration relating to image processing in the case of using a dual port memory in general.

10 is a block diagram showing a specific configuration of a conventional dual port memory.

11 is a timing chart for explaining the operation of a normal read transmission cycle in a conventional dual port memory.

12 is a timing chart for explaining the operation of the pseudolite transfer cycle in the conventional dual port memory.

13 is a schematic diagram showing an overview of a general field memory.

* Explanation of symbols for main parts of the drawings

2: memory cell array 4a and 4b: data register

5: Serial I / O buffer 6a and 6b: Serial Serecta

7: address pointer 10: address buffer

16: Timing generating circuit SWE ↓: External signal

A-Port: Random Access Port B-Port: Serial Access Port

(The same symbol in the drawing indicates the same or corresponding part.)

[Industrial use]

TECHNICAL FIELD This invention relates to a semiconductor memory device of the dual port which has a random access port serial access port especially with respect to a semiconductor memory device.

[Prior art]

In recent years, with the development of image processing technology, for example, color display on a CRT of a personal computer, processing of three-dimensional display, enlargement and reduction of an image in a CAD system, multi-window display and resolution Technology development for improvement is rapidly leading.

On the other hand, attention has also been paid to computer graphics for displaying numerical calculation results by spur computers.

Under such a situation, various video memory devices have been developed for storing digital image signals.

The dual port memory device is known as a random access memory optimized for storing image data, and random access and serial access are available at any time.

9 is a schematic diagram showing an outline of a dual port memory.

Referring to the drawings, a random-accessible dynamic memory cell array 101 for storing image data, a data transfer bus 102 for transferring data read from the memory cell array 101, and data for serial access. And a register (103).

The dynamic memory cell array 101 is connected to a central processing unit (CPU) 201 through a random access port and randomly accessed by the CPU 201.

On the other hand, the serial access data register 103 outputs the image data read through the data transfer bus 102 to the serial through the serial access port in response to the externally given serial clock signal SC. The output serial data is given to the CRT controller 202, and an image based on the serial data output on the CRT 203 is displayed.

FIG. 10 is a block diagram showing the configuration of the dual port memory shown in FIG.

Referring to the drawings, the dual port memory 100 includes a memory array 2 including memory cells MC arranged on a matrix, an address buffer 10 to receive address signals from the outside, and a row address signal AX0 to < RTI ID = 0.0 > Amplifying a row decoder 13 for specifying a word line WL in response to AX7, a column decoder 14 for selecting a pair of bit lines in response to the open-dress signals AY0 to AY7, and a data signal read out from a designated memory cell. The internal address signal SY0 for serial output based on the sense amplifier 3 for receiving, the data registers 4a and 4b for holding the amplified data signal, and the start addresses SA0 to SA7 given by the address buffer 10. To address points 7 for generating SY7, and serial selectors 6a and 6b for designating serial registers 4 in response to the generated internal address signals; to be.

The random access port (A-port) is connected to the data input / output buffer 15.

On the other hand, the serial access port (B-port) is connected to the serial input and output buffer (5). In the timing generating circuit 16, the row address strobe signal RAS ↓ (↓ means resiliency through this specification and drawings) is opened. The address of the strobe signal CAS ↓, the write bit signal WB ↓, the write designation signal WE ↓, and the data transmission. The signal DT ↓ / output enable signal OE ↓, the serial control signal SC and the serial enable signal SE ↓ are input. The timing generating circuit 16 generates the necessary control timing signals in response to these externally given signals.

Next, the operation will be briefly described.

Through the random access port, that is, parallel data input and parallel data output WTO, memory cells designated by the address signals AX and AY are randomly accessed.

On the other hand, serial data is input in response to the internal address signal generated by the address pointer 7 through the serial access port, i.e., the serial data input and serial data output SIO.

FIG. 11 is a timing chart showing the normalized transfer cycle of the dual port memory shown in FIG.

In the figure, the serial port before the transfer cycle is set in the write mode, and then data transfer is performed in the memory cell array to display various signal changes in the case of changing to the read mode.

After RAS ↓ is lowered, in response to the signal CAS ↓ being lowered, it is taken into the read address at the head of the serial access memory in the recording mode. Subsequently, predetermined data based on the read first address is transmitted to the data register, and is output through the serial access port as valid data in response to the change of the signal SC with the signal SE ↓ lowered.

FIG. 12 is a timing chart showing the pseudolite transfer cycle in the dual port memory of FIG.

In this case, the serial access port before the transfer cycle is set to the read mode, and the serial access port is set to change to the write mode by performing this pseudo write transfer cycle.

The pseudo SE is performed in the state of the "H" level, and the leading address for writing to the serial access memory is taken in response to the drop of the signal CAS ↓ following the drop of the signal RAS ↓. This SE ↓ signal is at the "L" level, and input data from the serial port is taken in response to a change in the signal SC.

In this way, the operation mode is changed, and then the data write operation is performed serially.

In recent years, in the field of video technology such as TV and VTR, the demand for digital signal processing for video signals has increased. In other words, digital TVs and digital VTRs are being developed. In these devices, the video signal is digitally processed to realize high image quality and multifunction.

Under such circumstances, a field memory has been developed for storing telephone data to be displayed on one screen.

13 is a schematic diagram showing an outline of a field memory.

Referring to the drawing, the field memory 300 includes a field memory cell array 303 for storing data for displaying one screen with the serial input register 301 for receiving serial data, and for holding output data. Serial output registers 305, data transfer buses 302 and 304;

The serial input register 301 receives data output from the A / D converter 204 through the serial input port in response to the clock signal SC1.

On the other hand, the serial output register 305, in response to the clock signal SC2, is given data read from the memory cell array 303 to the D / A converter 205 through the serial output port.

As described above, a dual port memory generally has two input / output units, namely, a random access port and a serial access port. In contrast, a field memory generally includes a serial input port and a serial output port.

It is pointed out that these two memory devices are common in that both output serially data read from the memory cell array in response to an externally given serial clock.

Since the serial output of the read data is performed in response to one serial lock signal, data for displaying an image or a video can be obtained at high speed.

[Problem to Solve Invention]

In the conventional dual port memory or field memory as described above, high-speed operation is possible for only one-input or output-only one-way serial input / output, but in use such as complicated input / output switching or in use such as field memory. In the case of processing the image data in the case of, it was not said that it is good to use.

In the conventional dual port memory, since the input and output of the serial access port are set after combining the transfer cycles as described above, it is necessary to execute transfer cycles (normally about 160 ns to 220 ns) to switch the mode of this operation.

Therefore, the input mode and the output mode could not be switched at any time during the serial access operation.

In addition, there is a problem that read / write / write / write / write operations in the serial access port cannot be executed because the transfer cycle is in between.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a dual port memory which can quickly switch the input / output mode in the dual port memory and facilitate the processing of data during this switching. It aims to do it.

A semiconductor memory device having dual ports consisting of a random access port (A port) and a serial access port (B port), the read mode setting means for setting the serial access port (B port) in a state that can be used for a read operation ( 16, And recording mode setting means for setting the serial access port (port B) in a state capable of being used for recording operation (16, ) And a prescribed signal from outside First signal generating means (16,) for generating a first signal according to And the electric read mode setting means 16 for switching to the read mode or the write mode of the electric serial access port (B port) in response to the generated first signal. In the present invention having control means 4a, 4b, and 5 for controlling), the read mode and the write mode are switched based on one signal generated.

EXAMPLE

1 is a block diagram showing the configuration of a dual port memory according to an embodiment of the present invention. In the drawings, the basic configuration is the same as that of the conventional dual port memory shown in FIG. 10, and the differences from the conventional example will be mainly described. As shown in the figure, the terminal is newly provided as a terminal connected to the timing generating circuit 16 so that the external signal SWE ↓ is input. Based on this external signal SWE ↓ change, the I / O mode of the serial access port is switched from time to time.

2 is a timing chart in the serial write operation according to an embodiment of the present invention. In this embodiment, the transfer cycle operation for transferring data from the memory cell array to the data register and the operation for switching the input / output mode of the serial access port are independent of each other. In the drawing, serial access ports are set to the output mode until n-1 of the memory cell array. In the serial access port, output data is sequentially output at address n-2 and address n-1. At this time, the external signal SWE ↓ is held at the "H" level, and in response to the rise of the serial enable signal SE ↓, input from the serial access port becomes possible. In response to the drop of the external signal SWE ↓, input data is drawn into the serial input / output buffer 5 as the data of the n address. In this way, the input / output operation mode of the serial access port can be easily switched only by the change of the external signal SWE ↓.

3 is a timing chart for explaining the operation of the serial lead modifier light according to one embodiment of the present invention. In the figure, the data of the memory array at the address of address n is drawn as the output data of address n into the data register with the signal SE? Next, the signal SE ↓ is converted from the "L" level to the "H" level; Again the signal SWE ↓ drops. As a result, the recording data given to the serial access port is put into the data register through the serial input buffer 5 as the write input data of the n address, and as a result, the address data of the n address is replaced. Subsequently, the SWE ↓ signal is raised to a high impedance state, and then the signal SE ↓ is lowered. As a result, data at address n + 1 is extracted as output data at address n + 1. In this way, only by changing the external signal SWE ↓ signal, read / write / write operation using the serial access port becomes possible.

4 is a timing chart for explaining the operation of the serial read according to one embodiment of the present invention. As shown in the figure, in the serial read operation, the serial access port is set only as the read mode, and the external signal SWE ↓ does not change as it is at the "H" level. Therefore, due to the drop of the signal SE ↓ and the rise of the signal SC, the data of the predetermined address is taken out as serial output data, and the serial data output is stopped in response to the rise of the signal SE ↓. Therefore, in normal serial read operation, normal serial operation is possible without changing the external signal SWE ↓.

5 is a block diagram when a dual port memory according to an embodiment of the present invention is applied to a specific apparatus. In the figure, the digital signal 21 in the television is branched to a multiplexer 23 and a switch circuit 27. The output of the switch circuit is input to the dual port memory consisting of the serial access memory 29 and the random access memory 31 constituting the dual port memory 100. The random access memory 100 and the CPU 33 are interconnected. The output of the switch circuit 27 is also output from the multiplexer 23. The output of the multiplexer 23 is output to the display device (CRT) 25. This apparatus is explained on the assumption that there are two types of digital signals in the television, data for A picture and data for B picture. As the operation in this case, first, the data of the A picture is stored in the RAM 31, and then, a part of the data of the B picture is written into the partial RAM 31, and the A picture stored in the RAM 31 again. The data of B and the data of the B picture are summed and displayed on the CRT 25.

6 is a timing chart for displaying the operation of the dual port memory in the case of performing such image processing. First, in the period T ₁ , by switching the switch circuit 27, the output of the data of the A image of the digital signal 21 on the television is output to the multiplexer 23 and the serial access memory 29 is output. It is stored in the RAM 31 through. In this state, the CRT is outputting data of the A picture. Next, in the period T ₁ , data of the B picture is output on the television. At this time, the switch circuit 27 outputs the B-picture data to the serial access memory 29. However, as shown in the figure, the external signal SWE ↓ drops only a part of the output of the data of the B picture, and the RAM 31 actually stores a part of the data of the B picture. At this time, the data of the B picture output through the multiplexer 23 is displayed on the front surface of the CRT 25. In this manner, in the period of T ₂ , some of the B-picture data is stored in the RAM 31. Next, on the substrate T ₃ , the data is read out serially and output to the multiplexer 23 in the RAM 31 which is stored in a state where the data of the A picture and the data of the B picture are stored in duplicate. That is, in this state, the external signal SWE ↓ is at the "H" level, and the serial access port is set to the read mode. When the image data read in this way is output to the CRT 25, as shown in the figure, an image in which part of the data of the B image overlaps with a part of the A image also in the CRT. In this way, the image data can be easily and quickly processed by using the dual port memory according to the present invention.

7 is a timing chart when a dual port memory is used for read, write and write operations according to one embodiment of the present invention.

FIG. 8 is a timing chart for explaining the operation when the read mode write operation is performed using the page mode in the conventional dual port memory.

Using FIG. 7 and FIG. 8, compare the time required to perform read, write, and write operations on successive rows.

As a whole, an operation of reading data of 100 consecutive bits from row A to column B of row R, and then writing new data into those bits is assumed.

In FIG. 7, the 1-bit read / modify / write cycle using the serial access port of the dual port memory according to one embodiment of the present invention is calculated as at least 60 ns.

That is, each time the signal SC rises, one bit of data is read and, in response to the drop of the signal SWE ↓, the data input from the serial access port is transferred to the recording operation.

In this manner, this read and write operation is performed for each 60 ns period. In the read mode cycle when the serial access port is used, read transfer and write transfer are required before and after performing the read operation and the write operation, but the time required for each transfer operation is 190 ns. Imagine.

In this way, in order to perform the read-modify / write operation of the predetermined column, the time required for the operation is 190 ns + 60 ns x 100 columns + 190 ns = 6.38 mW.

On the other hand, as shown in FIG. 8, in the conventional dual-port memory, when the read mode write operation is performed using the page mode, the read operation and the write operation are performed at 120 ns every time the signal CAS ↓ goes down. The operation is performed.

Therefore, the time required for performing the read mode write operation for a predetermined column is 120 ns x 100 columns = 12 ms.

Thus, by using the dual port memory according to one embodiment of the present invention, the time required for read, write, and write cycles is further shortened.

[Effects of the Invention]

As described above, the present invention switches the read mode and the write mode on the basis of one generated signal, so that the mode switching by the transfer cycle is unnecessary, and the input / output of the serial access port can be switched quickly.

Claims (6)

In a semiconductor memory device having dual ports consisting of a random access port (A port) and a serial access port (B port), a read mode setting for setting the serial access port (B port) in a state that can be used for a read operation. Sudan (16, And recording mode setting means (16) for setting the serial access port (port B) to a state that can be used for a recording operation. ) And a prescribed signal from outside A first signal generating means 16 for generating a first signal according to And the read mode setting means 16 for switching to the read mode or the write mode of the serial access port (port B) in response to the generated first signal. A semiconductor memory device having control means (4a, 4b, 5) for controlling (). 2. The second signal generating means (16) according to claim 1, wherein the second signal generating means (16) Is provided, and the control means 4a, 4b, 5 are provided with the recording mode setting means 16, ) Is released as a response to the first signal, and the read mode setting means 16, ) Is released as a response to the second signal. 3. The reading mode setting means (16) according to claim 2, wherein said control means (4a, 4b, 5) ) Is controlled only as a response to the second signal during its serial read operation. The method according to any one of claims 1 to 3, wherein the control means (4a, 4b, 5) is the read mode setting means (16). ) And recording mode setting means (16, ) Is controlled during their serial read-modify-write operation. The semiconductor memory device according to any one of claims 1 to 3, wherein said control means (4a, 4b, 5) include page mode control. A method for controlling read / write operations performed on / from a semiconductor memory having dual ports consisting of the random access port (A port) and the serial access port (B port), wherein the serial access port (B port). Setting the read mode to read the data, reading the data in accordance with the set read mode, generating a signal to be an external signal applied to the semiconductor memory device, and the serial access. And setting the recording mode instead of the read mode as a response to the signal generated by the port (port B) to record data, and recording the data in accordance with the set recording mode.