JPH04274082A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To quickly switch an input/output mode by switching the mode of serial access port in response to one generated signal. CONSTITUTION:On a RAM 100 provided with a memory cell array 2, the serial access port B-port as well as a randum access port A-port is provided. In response to signals SWE generated by a timing generating circuit 16, a serial input/output buffer 5 is controlled and the port B-port is switched to a write mode or a read mode. By the mode through this one signal SWE, in the semiconductor memory device having a dual port, the switching of the input/output mode in the input/output port of the seial port is quickly switched.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dual-port semiconductor memory device having a random access port and a serial access port.

0002

[Background Art] With the recent development of image processing technology, for example, color display on CRT of personal computers, three-dimensional display in CAD systems, processing such as enlargement and reduction of images, multi-window display, and improvement of resolution. Technology development is progressing rapidly. In addition, computer graphics for displaying numerical calculation results by supercomputers are also attracting attention. Under these circumstances, various video memory devices have been developed for storing digital image signals. Dual port memory devices are known as optimized random access memories for storing image data, allowing random access and serial access at any time.

FIG. 9 is a schematic diagram showing an overview of a dual port memory. Referring to the figure, a randomly accessible dynamic memory cell array 101 for storing image data, a data transfer bus 102 for transferring data read from the memory cell array 101, and a data register 103 for serial access are shown. include. Dynamic memory cell array 101 is connected to central processing unit (CPU) 201 through a random access port,
It is randomly accessed by the CPU 201.

On the other hand, the serial access data register 103 receives an externally applied serial clock signal S.
In response to C, the image data read out through the data transfer bus 102 is serially outputted through the serial access port. The output serial data is given to the CRT controller 202, and an image based on the output serial data is displayed on the CRT 203.

FIG. 10 is a block diagram showing the configuration of the dual port memory shown in FIG. 9.

Referring to the figure, this dual port memory 100 includes memory cells MC arranged in a matrix.
a memory cell array 2 including a memory cell array 2, an address buffer 10 for receiving address signals from the outside, a row decoder 13 for specifying a word line WL in response to row address signals AX0 to AX7, and column address signals AY0 to AY.
Column decoder 1 for selecting a bit line pair in response to
4, a sense amplifier 3 for amplifying a data signal read from a designated memory cell, data registers 4a and 4b for holding the amplified data signal, and a start address S given from an address buffer 10.
An address pointer 7 that generates internal address signals SY0 to SY7 for serial output based on A0 to SA7, and serial selectors 6a and 6b to specify the serial register 4 in response to the generated internal address signals. It includes. The random access port (A-Port) is a data input/output buffer 15
connected to. On the other hand, the serial access port (B-P
ort) is connected to the serial input/output buffer 5.

The timing generation circuit 16 includes a row address strobe signal RAS↓ (↓ means a negative activation signal throughout this specification and drawings), a column address strobe signal CAS↓, and a write bit signal WB↓/write designation. Signal WE↓
, data transfer signal DT↓/output enable signal OE↓,
A serial control signal SC and a serial enable signal SE↓ are input. Timing generation circuit 16 generates necessary control timing signals in response to these externally applied signals.

Next, the operation will be briefly explained. Via the random access port, i.e. parallel data input and parallel data output WIO, the address signal AX
The memory cells designated by and AY are randomly accessed. On the other hand, the serial access port, i.e. serial data input and serial data output SI
Serial data is input/output via O in response to an internal address signal generated by address pointer 7.

FIG. 11 is a timing chart showing a normal read transfer cycle of the dual port memory shown in FIG.

In the figure, the serial port is set to write mode before a transfer cycle, and then data is transferred from the memory cell array, and changes in various signals are shown when changing to read mode. There is.

After RAS↓ falls, the first read address of the serial access memory in the write mode is taken in in response to the fall of signal CAS↓. Next, predetermined data based on the read start address is transferred to the data register, and is output as valid data through the serial access port in response to a change in the signal SC while the signal SE↓ is falling. Ru.

FIG. 12 is a timing chart showing a pseudo write transfer cycle in the dual port memory of FIG. In this case, the serial access port before the transfer cycle is set to read mode, and by performing this pseudo write transfer cycle, the serial access port is set to write mode.

Pseudo write transfer is performed when signal SE↓ is at “H” level, and in response to the fall of signal CAS↓ following the fall of signal RAS↓, the start address for writing to the serial access memory is determined. is taken in. This S
With the E↓ signal at the "L" level, input data is taken in from the serial port in response to a change in the signal SC. The operation mode is changed in this manner, and data write operations are subsequently performed serially.

Incidentally, in recent years in the field of video technology such as televisions and video tape recorders (VTRs), there has been an increasing demand for digital signal processing for video signals. That is, digital televisions, digital VTRs, and the like are being developed. These devices achieve higher image quality and multifunctionality of images by digitally processing video signals. Under these circumstances, field memories have been developed to store all image data to be displayed on one screen.

FIG. 13 is a schematic diagram showing an overview of the field memory. Referring to the figure, field memory 300
includes a serial input register 301 for receiving serial data, a field memory cell array 303 for storing data for displaying one screen, a serial output register 305 for holding output data, and a data transfer bus 302. and 304. In response to the clock signal SC1, the serial input register 301
The data output from the A/D converter 204 is taken in via the serial input port. On the other hand, serial output register 305 provides data read from memory cell array 303 to D/A converter 205 via a serial output port in response to clock signal SC2.

As mentioned above, a dual port memory generally has two input/output sections: a random access port and a serial access port. In contrast, field memories typically have a serial input port and a serial output port. It is pointed out that these two memory devices have in common that they both serially output data read from a memory cell array in response to an externally applied serial clock. Since serial output of read data is performed in response to one serial clock signal, data for displaying an image or video can be obtained at high speed.

[0017]

[Problems to be Solved by the Invention] Conventional dual-port memories and field memories as described above are capable of high-speed operation for unidirectional serial input/output of input only or output only. It cannot be said that it is easy to use when the output is to be changed in a complicated manner or when image data is to be processed when used as a field memory.

[0018] Conventional dual port memory incorporates a transfer cycle as described above and then sets the input/output of the serial access port, so switching the operation mode requires a transfer cycle (usually about 160ns to 220ns). ) must be executed. Therefore, during continuous serial access operations, it is not possible to switch between the input mode and the output mode at any time.

[0019] Further, there is a problem that a read/modify/write operation for rewriting after reading at a serial access port cannot be executed because a transfer cycle occurs during that period.

The present invention was made in order to solve the above-mentioned problems, and it is possible to speed up the input/output mode switching operation in a dual port memory and to facilitate data processing at the time of switching. The purpose is to provide dual-port memory that can be used.

[0021]

[Means for Solving the Problems] A semiconductor memory device according to the present invention has a dual port consisting of a random access port and a serial access port, and the serial access port is set to be used for a read operation. read mode setting means; write mode setting means for setting the serial access port to be used for a write operation; signal generation means for generating a signal 1; The control means controls the read mode setting means and the write mode setting means so as to switch the mode of the serial access port.

[0022]

In the present invention, the read mode and write mode are switched based on the generated 1 signal.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of a dual port memory according to an embodiment of the present invention.

In the figure, the basic configuration is the same as that of the conventional dual port memory shown in FIG. 10, so the differences from the conventional example will be mainly explained.

As shown in the figure, the timing generation circuit 16
A new terminal to which the external signal SWE↓ is input is provided as a terminal connected to the external signal SWE↓. This external signal S
The input/output mode of the serial access port is switched at any time based on the change in WE↓.

FIG. 2 is a timing chart of a serial write operation according to an embodiment of the present invention.

In this embodiment, the transfer cycle operation for transferring data from the memory cell array to the data register and the operation for switching the input/output mode of the serial access port are made separate and independent. In the figure, the serial access port is set to output mode up to address n-1 of the memory cell array, and from the serial access port, n-2
The output data of address n-1 is being output. At this time, the external signal SWE↓ is kept at “H” level,
Next, in response to the rise of the serial enable signal SE↓, input from the serial access port becomes possible. Then, in response to the fall of the external signal SWE↓, the input data is taken into the serial input/output buffer 5 as data at address n. In this way, the external signal SW
The input/output operation mode of the serial access port can be easily switched only by changing E↓.

FIG. 3 is a timing chart for explaining the operation of serial read/modify/write according to an embodiment of the present invention.

In the figure, data in the memory cell array at address n is taken out to the data register as output data at address n while signal SE↓ is at the "L" level. Next, after the signal SE↓ changes from the "L" level to the "H" level, the signal SWE↓ further falls. As a result, the write data given to the serial access port is taken into the data register via the serial input buffer 5 as write input data at address n, and as a result, the address data at address n is rewritten. Become. Subsequently, the SWE↓ signal rises to a high impedance state, and then the signal SE↓ falls. As a result, the data at address n+1 is taken out as output data at address n+1.

[0030] In this way, read/modify/write operations using the serial access port can be performed simply by changing the external signal SWE↓ signal.

FIG. 4 is a timing chart for explaining the serial read operation according to an embodiment of the present invention.

As shown in the figure, in the serial read operation, the serial access port is set only in read mode, so the external signal SWE↓ remains at the "H" level and does not change. Therefore, data at a predetermined address is serially taken out as output data by the fall of the signal SE↓ and the rise of the signal SC, and serial data output is stopped in response to the rise of the signal SE↓. Therefore, in a normal serial read operation, normal serial operation is possible without changing the external signal SWE↓.

FIG. 5 is a block diagram when a dual port memory according to an embodiment of the present invention is applied to a specific device.

In the figure, a digital signal 21 from a television is sent to a multiplexer 23 and a switch circuit 27.
A branch output is made. The output of the switch circuit is the serial access memory 2 that constitutes the dual port memory 100.
9 and a random access memory 31. random access memory 10
0 and CPU 33 are interconnected. The output of the switch circuit 27 is also output to the multiplexer 23. The output of the multiplexer 23 is connected to a display device (C
RT) 25.

This apparatus will be explained on the premise that there are two types of digital signals from the television: A-picture data and B-picture data. The operation in this case is to first store the A image data in the RAM 31, then partially write some of the B image data to the RAM 31, and then write the A image data and B image data stored in the RAM 31. It is intended to display both on the CRT 25.

FIG. 6 is a timing chart showing the operation of the dual port memory when performing such image processing.

First, in the period T1, the output of image A data of the digital signal 21 from the television is changed to the multiplexer 23 by switching the switch circuit 27.
The data is output to the RAM 31 via the serial access memory 29 and stored in the RAM 31 . In this state, data of image A is being output to the CRT.

Next, during period T2, B image data is output from the television. At this time, the switch circuit 27 outputs the B image data to the serial access memory 29. However, as shown in the figure, since the external signal SWE↓ falls only partially during the output of the B image data, it is assumed that part of the B image data is actually stored in the RAM 31. become. At this time, the B image data outputted via the multiplexer 23 is displayed on the entire surface of the CRT 25. In this way, during the period T2, the RAM 31 is in a state where part of the data of the B image is stored.

Next, during period T3, the data of the A image and the data of the B image are serially read out from the RAM 31 in which the data are stored in a superimposed state and are output to the multiplexer 23. That is, in this state, the external signal SWE↓ is at the "H" level, and the serial access port is set to the read mode. The image data read out in this way is
25, an image in which part of the data of the B image is superimposed on a part of the A image is output even on the CRT, as shown in the figure. In this way, by using the dual port memory according to the present invention, image data can be processed easily and quickly.

FIG. 7 is a timing chart when a dual-port memory according to an embodiment of the present invention is used for read-modify-write operations, and FIG. - This is a timing chart for explaining the operation when a write operation is performed.

The time required to perform read/modify/write operations on consecutive columns will be compared using FIGS. 7 and 8.

As a premise, it is assumed that after reading data of bits in 100 consecutive columns from column A to column B of row R, new data is written to those bits.

In FIG. 7, a 1-bit read-modify-write cycle using the serial access port of a dual-port memory according to an embodiment of the present invention is as follows:
Calculated assuming a minimum of 60 ns. That is, one bit of data is read every time the signal SC rises, and in response to the fall of the signal SWE↓, the operation shifts to writing the data input from the serial access port. In this way, the read and write operations are performed every 60 ns. In the read-modify cycle when using a serial access port, read transfer and write transfer are required before and after the read and write operations, but the time required for each transfer operation is Assume the time is 190ns. In this way, when performing a read/modify/write operation on a predetermined column, the time required for the operation is 190ns + 60ns x 100 columns + 190ns = 6
．． It becomes 38 μs.

On the other hand, as shown in FIG. 8, in a conventional dual port memory, read/write is performed using page mode.
When performing a modify write operation, a read operation and a write operation are performed every fall (120 ns) of the signal CAS↓. Therefore, the time required to perform a read/modify/write operation on a predetermined column is 120 ns×100 columns=12 μs.

As described above, by using the dual port memory according to an embodiment of the present invention, the time required for the read/modify/write cycle is further reduced.

[0046]

Effects of the Invention As described above, the present invention switches between the read mode and the write mode based on the generated 1 signal, eliminating the need for mode switching based on the transfer cycle, and improving the input/output of the serial access port. The switching is done quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a dual port memory according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining a serial write operation by the dual port memory of FIG. 1;

FIG. 3 is a timing chart for explaining serial read/modify/write operations by the dual port memory of FIG. 1;

FIG. 4 is a timing chart for explaining a serial read operation by the dual port memory of FIG. 1;

FIG. 5 is a block diagram showing a configuration when image processing is performed using a dual port memory according to an embodiment of the present invention.

FIG. 6 is a timing chart for explaining the image processing operation shown in FIG. 5;

FIG. 7 is a timing chart for explaining the time required for read/modify/write operations when using a dual port memory according to an embodiment of the present invention.

FIG. 8 is a timing chart for explaining the time required for read/modify/write operations using page mode in a conventional dual-port memory.

FIG. 9 is a block diagram showing a configuration related to image processing when a general dual port memory is used.

FIG. 10 is a block diagram showing a specific configuration of a conventional dual port memory.

FIG. 11 is a timing chart for explaining the operation of a normal read transfer cycle in a conventional dual port memory.

FIG. 12 is a timing chart for explaining the operation of a pseudo write transfer cycle in a conventional dual port memory.

FIG. 13 is a schematic diagram showing an overview of a general field memory.

[Explanation of symbols]

2 Memory cell arrays 4a and 4b Data register 5 Serial input/output buffers 6a and 6b Serial selector 7 Address pointer 10 Address buffer 16 Timing generation circuit SWE↓ External signal A-Port Random access port B-Port
Serial Access Port Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor memory device having a dual port consisting of a random access port and a serial access port, comprising read mode setting means for setting the serial access port to be used for a read operation; write mode setting means for setting to be used for a write operation; signal generation means for generating a signal 1; and a mode of the serial access port being set in response to the generated signal 1; A semiconductor memory device comprising: control means for controlling the read mode setting means and the write mode setting means so as to switch between the read mode setting means and the write mode setting means.