JP2710926B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory suitable for use in a frame buffer of a bitmap display. 2. Description of the Related Art Conventionally, a semiconductor memory used for a frame buffer of a bit map display needs to read or write a large amount of pixel bit data at high speed, and therefore has a plurality of access means. Devices capable of simultaneously performing random access and serial access have been developed. As an example of this type of semiconductor memory, see Nikkei Electronics, May 20, 1985, No. 195-1985.
Page 219 “256K for images where domestic and foreign manufacturers enter at the same time
Some are discussed in the literature entitled "Dual Port Memory." FIG. 6 shows the internal block diagram of a dual port memory without a serial input function, and FIG. 10 shows the internal block diagram of such a dual port memory. An operation timing chart when a serial input function is added is shown. [0005] The serial input function shown here is:
This is realized by stopping the serial output, switching the serial port to the output mode, serially inputting write data of an arbitrary length to the serial data register, and executing a data transfer cycle from the serial data to the memory cell array. By using this function, arbitrary plural bits can be written simultaneously. Further, by executing the data transfer cycle continuously for different row addresses, an arbitrary rectangular area can be cleared at high speed. It becomes possible. FIG. 13 on page 215 of the above-mentioned document shows an internal block diagram of a dual port memory capable of executing simultaneous writing of a plurality of bits without stopping serial output. In the method shown here, a selector for switching between a serial data register and input data from a random port is provided, and the selector is designated to a mode for selecting input data from a random port by a column address in a data transfer cycle. At the same time, by simultaneously specifying the bit length and the column address, simultaneous writing of a plurality of bits is realized without stopping the serial output. In this case, serial input of write data to the serial data register is unnecessary, but since the bit length is specified using a column address signal,
The bit length is limited to four types of 16, 32, 64 and 128 bits. Also in this case, it is possible to clear the above-described four bit-length rectangular areas at high speed by continuously executing data transfer cycles for different row addresses. However, when the dual port memory as shown in the prior art is used for a frame memory buffer of a bitmap display having a multi-window function, the serial output is interrupted. No consideration is given to the necessity of clearing a rectangular area (window) having an arbitrary bit length at high speed without performing the above operation. That is, as described in the prior art, in the method shown in FIG. 10 on page 210 of the above-mentioned document, the memory cell is cleared during serial output (for performing simultaneous writing of a plurality of bits). Serial input of data and internal data transfer cannot be performed), and the clear operation must be executed by selecting a timing such as a retrace period during which the memory does not perform serial output, and the clear operation cannot be performed at high speed. was there. In addition, the method shown in FIG. 13 on page 215 of the above-mentioned document has a problem that the number of simultaneous write bits is limited to four, and an area having an arbitrary bit length cannot be cleared. . SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. It is an object of the present invention to quickly clear an area having an arbitrary bit length with a simple circuit configuration in a semiconductor memory. It is to provide a technology that makes it possible. Another object of the present invention is to provide a technique that enables a region to be cleared in a semiconductor memory to be set at a high speed without adding a new configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Means for Solving the Problems Of the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. (1) A storage unit in which a plurality of storage elements are arranged in rows and columns, a column decoder for decoding a column address input via a signal line, and a storage area corresponding to a column position of the storage unit. A first register for holding a first column position that is a start point of a write permission area for writing to the storage means and a second column position that is one step ahead of a column position that is an end point; A write flag generation circuit comprising an exclusive-OR circuit for generating a flag that sets a region between the start point and the end point as a write-permitted area from the first column position and the second column position held in the register; Temporary storage means for temporarily storing a flag indicating whether or not writing to the storage means generated by the write flag generation circuit is possible, and simultaneously selecting a plurality of column positions for writing according to the flag of the temporary storage means, Writing A semiconductor memory for writing simultaneously transferring data only in the column direction of the storage means, said first
Is a first column position, which is a start point of a permission area to be input to the storage means through the signal line, which is output from the column decoder, and a column position which is an end point, which is increased by one. A first column position that is a start point of the write-permitted area to the storage unit and a second column position that is one end of the column position that is an end point based on the decoding result of the column address indicating the second column position. Is set. According to the means of (1), the column decoder is configured to set one column position as a start point and one column position as an end point of the permission area to the storage means inputted via the signal line. A column address indicating the advanced second column position is decoded, and based on the decoding result, a first register having a storage area corresponding to the column position of the storage unit stores a start point of the write permission area for the storage unit. Setting and holding a certain first column position and a second column position obtained by advancing the end point column position by one,
A write flag generation circuit generates, from the first column position and the second column position held in the first register, a flag for setting the area between the start point and the end point as a write permission area. The generated flag indicating whether or not writing to the storage means is temporarily stored in the temporary storage means, a plurality of column positions to be written are simultaneously selected according to the flag of the temporary storage means, and the write data is simultaneously stored in the column direction of the storage means. Since the data is transferred and written, it is possible to simultaneously write an arbitrary bit length in the column direction of the storage means with a simple circuit configuration without newly adding a configuration for specifying an area to be cleared. Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted. [First Embodiment of the Invention] FIG. 1 is an internal block diagram showing a schematic configuration of a semiconductor memory according to an embodiment of the present invention (first embodiment of the present invention). In FIG. 1, a column decoder 1 decodes a column address (AY) and outputs output signals (Y0 to Y25).
5) and output signals (Y0 to Y) from the column decoder 1.
255) is input to both the pointer register 3 and the selector 6. In the pointer register 3, the corresponding bit of the pointer register 3 is set to "1" by one selected signal among the output signals (Y0 to Y255) from the column decoder 1. The pointer register 3 shown in FIG. 1 shows a state where, for example, such a pointer set cycle is executed twice and the Y1 and Y5 bits of the pointer register 3 are set to "1". I have. The write flag generation circuit 4 receives the output signal from the pointer register 3 as an input, and
This is a circuit for successively setting "1" between the bits set to "1", and is constituted by an exclusive OR gate 12, as shown in FIG. The operation of the write flag generation circuit 4 is such that the exclusive OR gate 12 takes the exclusive OR of the Y0th output of the pointer register 3 and the Y1th output of the pointer register 3 and outputs the result. Is the Y1th output of the write flag generation circuit 4, and the exclusive OR of the Y1 output of the write flag generation circuit 4 and the Y2th output of the pointer register 3 is calculated by the exclusive OR gate 12. Then, the output is set as the Y2th output of the write flag generation circuit 4, and similarly, the output is performed up to the Y255th output of the pointer register 3 corresponding to the output signal from the column decoder 1, thereby obtaining "1". Is continuously set to "1" (flag setting state). The write flag register 5 is a circuit for holding an output signal from the write flag generation circuit 4.
An output signal (flag) from the write flag generation circuit 4 is latched by a flag set signal (FSET). The write flag register 5 shown in FIG. 1 uses the outputs from the Y1 and Y5 of the pointer register 3 to indicate that a flag has been generated successively to the Y1 to Y4th bits of the write flag register 5. Is shown. Here, it should be noted that the end point pointer (Y5 in FIG. 1) sets a pointer to an end point bit for which a flag is to be set, that is, a column address one address ahead of the last column address of a bit string to be simultaneously written. It is necessary. The selector 6 is a circuit for selecting and outputting one of the output signal of the write flag register 5 and the output signal of the column decoder 1, and is controlled by a selection signal (SEL). The data transfer gate 7 opens the gate corresponding to the bit selected by the write flag register 5 selected by the selector 6 or the output signal from the column decoder 1, and transfers the write data (DIN) to the memory cell array 8
To enter. The row decoder 9 decodes a row address (AX) and outputs output signals (X0 to X255). The memory cell array 8 includes a row line designated by one of the output signals (X0 to X255) from the row decoder 9 and a column line selected by the data transfer gate 7. Write data (DIN) is written to the memory cell at the intersection. The serial data register 10 and the data selector 11 store read data (S
D) is a circuit for controlling D), and is the same as the dual port memory in the prior art, so that the description is omitted. FIG. 2 is a time chart showing the operation of the semiconductor memory shown in FIG. Next, with reference to FIG. 2, an operation example of simultaneous writing of a plurality of bits in the semiconductor memory shown in FIG. 1 will be described. In FIG. 2, a row address strobe signal (RAS: hereinafter, referred to as RAS), a column address strobe signal (CAS: hereinafter, referred to as CAS), a write enable signal (WE: hereinafter, referred to as WE). , A block write designation signal (BW: hereinafter, referred to as BW) is a control signal given from the outside, and is input to the control circuit 2. Since RAS, CAS, and WE are control signals well known to those skilled in the art as control signals for general MOS dynamic memories, detailed description of the basic operations of RAS, CAS, and WE will be omitted. BW is a signal for distinguishing a simultaneous write mode of a plurality of bits from a normal operation mode. FIG. 3 is a diagram showing a combination of signal levels defining the operation of the time chart shown in FIG. 2, and corresponds to each cycle of an operation mode required to execute simultaneous writing of a plurality of bits. C at falling of RAS
It shows the signal level states of AS, WE, and BW. In order to distinguish each operation cycle, CAS
And the WE signal level. The operation of the semiconductor memory according to the first embodiment of the present invention will be described with reference to the time chart of FIG. First, in the reset cycle, when RAS falls, it is detected that CAS, WE, and BW are all at the low level, and a reset signal (RST) is generated.
The pointer register 3 is reset. Next, in pointer set cycle 1, R
When AS falls, CAS and WE are at High level,
After detecting that BW is at the Low level, at the fall of RAS, the column address (AYi) is fetched, decoded by the column decoder 1, and the bit selected by the column address (AYi) of the pointer register 3 is set to "1". That is, the pointer is set to the bit selected by the column address (AYi) of the pointer register 3. Similarly, in the pointer set cycle 2, the column address (AYi) is fetched and set in the pointer register 3. As described above, in the semiconductor memory according to the first embodiment of the present invention, when the start point pointer and the end point pointer are set in the pointer register 3, the column address line and the column decoder 1 used in the conventional semiconductor memory are used. Since it can be set by using, there is no need to add a new configuration to the semiconductor memory, and since it can be set in two cycles of the pointer set cycle 1 and the pointer set cycle 2, it is possible to set at high speed. is there. In the flag generation cycle, when RAS falls, CAS and BW are at low level, and WE is at high level.
Level, and when RAS falls,
A flag set signal (FSET) is generated, and the flag generated by the write flag generation circuit 4 is latched in the write flag register 5. Next, in the write cycle, when RAS falls, CAS goes high and WE and BW go low.
w level and the row address (A
Xm) is fetched, decoded by the row decoder 9, and simultaneously writes the write data (DIN) to the column of a plurality of bits specified by the write flag register 5 on the specified row line. At this time, a selector selection signal (SEL) is generated from the control circuit 2, and the selector selection signal (SEL) is generated.
Accordingly, the selector 6 selects the output signal of the write flag register 5. As shown in FIG. 2, this write cycle can be continuously executed for different next row addresses (AXm). As described above, according to the semiconductor memory of the first embodiment of the present invention, for example, the simultaneous writing operation of M bits in the continuous column direction is sequentially repeated while increasing the row address by +1 to obtain M × N All of the bit rectangular areas can be set to “0” or “1”. That is, an M × N rectangular area can be cleared at high speed. Since this operation is controlled on all random ports, it can be executed asynchronously independently of the operation of the serial port. [Embodiment 2] FIG. 4 is an internal block diagram showing a schematic structure of a semiconductor memory according to another embodiment (Embodiment 2) of the present invention. In FIG. 4, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will not be repeated. In the semiconductor memory shown in FIG. 4, instead of connecting the output of the column decoder 1 to the input terminal of the pointer register 3, read data (RD0 to RD255) for one row of the output of the memory cell array 8 is connected. This is different from the semiconductor memory shown in FIG. In such a configuration, the setting of the column address pointer in the pointer register 3 is performed by writing pointer data in an arbitrary row of the memory cell array 8 and
The setting can be made by simultaneously transferring the read data (RD0 to RD255) for one row to the pointer register 3. FIG. 5 is a time chart showing the operation of the semiconductor memory shown in FIG. Next, an operation example of simultaneous writing of a plurality of bits in the semiconductor memory shown in FIG. 4 will be described with reference to FIG. In normal write cycle 1, when RAS falls, it is detected that BW is at a high level, and a normal write operation is performed. That is, the pointer is written to the memory cell selected by the row address (AXr) and the column address (AYi). Similarly, in normal write cycle 2, a pointer is written to a memory cell selected by a row address (AXr) and a column address (AYj). Next, in the pointer set cycle, RA
When S falls, BW goes low, CAS, WE
Is high level, and fetches the row address (AXr). When the row decoder 9 decodes the row address (AXr) and selects one row of the memory cell array 8, the data of the memory cell 13 connected thereto is read. Here, CAS is changed from High level to Lo.
By setting it to the w level, the pointer set signal (PS
ET), and one line of read data (RD0-R
D255) is set in the pointer register 3. The operation after the next flag generation cycle is the same as the operation of the semiconductor memory according to the first embodiment of the present invention. As described above, in the semiconductor memory according to the second embodiment of the present invention, similar to the semiconductor memory according to the first embodiment, simultaneous writing of an arbitrary plurality of bits can be executed. In each of the embodiments of the present invention, the case where the memory cell array 8 is 256 × 256 has been described, but it is needless to say that the present invention is not limited to this. Although the description has been given of the case where the input of the write data is one bit, the present invention is not limited to this, and the same can be realized in the case of a multi-bit configuration. The pointer setting of the pointer register 5 has been described for the case of two points, the start point and the end point. However, the present invention is not limited to this. It is possible to set more pointers than points. Further, the pointer set cycle can be executed at high speed by using a conventionally known page mode operation. It goes without saying that the combinations of the signals shown in FIGS. 2 and 3 are not limited to these. Further, a block write designation signal (BW)
Are used for convenience of description, and can be substituted by a combination of timings of only signals used in a conventional dual port memory. As described above, the present invention has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the embodiments of the present invention, and various modifications may be made without departing from the gist of the present invention. It goes without saying that you get it. The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, in a semiconductor memory, a simultaneous writing range of a plurality of consecutive bits in a column direction is set by a start point and an end point pointer, and simultaneous writing of an arbitrary plurality of bits in a column direction of the memory can be performed. Since it is made possible, an area of an arbitrary bit length can be cleared at high speed. Since the simultaneous writing of an arbitrary plurality of bits in the column direction can be performed continuously in the column direction,
Any rectangular area can be cleared at high speed. (2) According to the present invention, in a semiconductor memory, a new configuration is added to a conventional semiconductor memory with start point and end point pointers for setting a simultaneous write range of a plurality of consecutive bits in a column direction. And can be set at high speed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an internal block diagram illustrating a schematic configuration of a semiconductor memory according to an embodiment (Embodiment 1) of the present invention; FIG. 2 is a time chart illustrating an operation of the semiconductor memory illustrated in FIG. 1; FIG. 3 is a diagram showing combinations of signal levels that define the operation of the time chart shown in FIG. 2; FIG. 4 is an internal block diagram showing a schematic configuration of a semiconductor memory according to another embodiment (Embodiment 2) of the present invention; FIG. 5 is a time chart illustrating an operation of the semiconductor memory illustrated in FIG. 4; [Description of Signs] 1 ... column decoder, 2 ... control circuit, 3 ... point register, 4 ... write flag generation circuit, 5 ... write flag register, 6 ... selector, 7 ... data transfer gate, 8 ... memory cell array, 9 ... Row decoder, 10 ... serial data register, 11 ... data selector.

Claims (1)

(57) [Claims] A storage unit having a plurality of storage elements arranged in rows and columns, a column decoder for decoding a column address input through a signal line, and a storage area corresponding to a column position of the storage unit; The first column position which is the start point of the write permission area for writing to the second column, and the second column position where the column position which is the end point is advanced by one.
A first register holding the column position of the first register and a first column position and a second column position held in the first register, a flag indicating that the area between the start point and the end point is a write-permitted area. A write flag generation circuit including an exclusive OR circuit for generating the write flag; and a temporary storage unit for temporarily storing a flag generated by the write flag generation circuit, the flag indicating whether or not writing to the storage unit is possible. A plurality of column positions to be written are simultaneously selected according to the flag of the means,
A semiconductor memory for simultaneously transferring and writing write data in a column direction of a storage unit, wherein the first register is configured to enable the storage unit to be output from the column decoder and input through the signal line to the storage unit. Based on the decoding result of the column address indicating the first column position which is the start point of the area and the second column position which is one step ahead of the column position which is the end point, it is the start point of the write permission area to the storage means. A semiconductor memory, wherein a first column position and a second column position that is one step ahead of the end column position are set.