SU1531103A1 - Device for interfacing between computer, permanent storage and external storage - Google Patents

Abstract

The invention relates to computing and can be used in the design of computing systems. The purpose of the invention is to increase the speed and reduce the amount of equipment of the device. The device contains a bidirectional switch 1, information counter 2, state register 3, first 4, second 5 address counters, control block 6, buffer register 7, address 8 and information multiplexers 9. The device provides the processor access mode of the main memory and forward external storage access to RAM. 1 hp ff, 2 ill.

Description

ate

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mutator 1, information counter 2, status register 3, first 4, second address counters, control block 6, buffer register 7, address 8 and information multiplexers 9. Device / gvo

provides the processor access mode to the RAM and direct access of the external storage device to the RAM. 1 h, para. f-ly, 2 ill.

The invention relates to computing and can be used in the design of computing systems.

The aim of the invention is to improve speed.

FIG. 1 is a block diagram of the device; in fig. 2 is a control block diagram.

FIG. 1 shows a bidirectional switch 1, information counter 2, state register 3, first 4, second 5 address counters, control block 6, buffer register 7, address multiplexers 8 and information 9, external storage device 10, random access memory 11, first 12, second 13 outputs of control unit 6, first input 14, information input-output 15 and third output 16 of control unit 6, eleven output 17 of control unit 6, second input 18, fourth 19, fifth 5 outputs of control unit, information outputs 21 and 22 of the first 4 and second 5 counters of the address My 23, sixth 24, ten 25, ninth 26 and seventh 27 outputs of control unit 6, first 28 and second 29 information inputs of multiplexer 8 address, first information input 30, information output 31, second information input 32 of buffer register 7 , output 33g-1t multiplexer address.

:

FIG. 2 shows a block of 34 NAND elements, a block of 35 receivers, a perviCTp of 36 signs, a first decoder 37, a decoder 38 commands, a block of 39 OR elements, a register 40, a single vibrator 41, a counter 42, a block 43 of transmitters, a second decoder 44, a block 45 triggers, block 46 selectors.

The device has two main modes of operation: the processor access mode to the operating memory (SP) and the direct access mode of the external storage device (OVC) to the RAM.

In the mode of the processor accessing the OP, the FOR block of the NAND elements, when the OP address code arrives at the inputs 15, generates a signal of the OP sign, which after 1 falls on the register 36 of signs, where when the corresponding main signals are received through the block 35 receivers of the corresponding main signals, OP records, These signals through a block of 39 elements OR trigger a single vibrator 41, the output of which goes to the counting input of counter 42, the outputs of which go to the code inputs of the decoder 44, which outputs a series of clock signals. The trigger unit 45, in the presence of a read indicator, under the control of the corresponding clocking outputs, generates an OP sample signal, while in the presence of an OP recording, the trigger unit 45 also generates an OP recording signal.

The OP address from the trunk is received at the memory multiplexer 8 of the address (input 29) under the control of signals from the selector unit 46.

The information when reading the EI arrives at the trunk via the bi-directional switch 1, the transmission direction of which is determined by the output 12 of the register of 36 signs. When recording OP information, the information inputs OP arrives through information multiplexer 9, controlled by signals generated by the selector unit 46.

In the direct access mode, the device organizes the exchange of information between the PD and the OVC. To do this, the initial addresses of the POS and the OVC, respectively, are entered into the counters 4 and 5 of the address, respectively, and the length of the sent array is entered into the counter 2 of the information. In register 3, states after entering information into counters 2.4 and 5, the command code is entered, the decryption codec 38 decoder and the start command are entered.

A block of 34 NAND elements upon receipt of one of the address 2 counters,. 4 and 5 or state register 3 generates a signal enabling the operation of the

51

the encoder 37 addresses, providing address access to the counters 2,

4n 5, or register 3 states. The outputs of the decoder 37 are received on the block

39 OR elements, where, in the event of a recording feature coming from the trunk through the receiver block 35, a strobe signal is generated, through which information is received, received from the trunk. After writing the state of the command code and the start command to the register 3, the register 40 forms a request for the trunk, which is received through the transmitter unit 43 to the output 1 5.

The capture enable signal from the inputs / outputs 15 through the receiver unit 36 is transmitted to the register 40, where a request confirmation signal is generated, which is simultaneously the signal to start the exchange. Thus, the trunk is occupied at the time of the exchange of information, if it is carried out via direct links, mine trunk. The signal for 1 request query starts the one-shot 41.

If in the state register 3 the code of the command of write OCU is recorded, the block 45 of the flip-flops, controlled by the corresponding clock outputs of the decoder 44, generates signals of the OP sample and the sample and write of the OVC. Address OP comes from the output 21 of the counter 4 through the multiplexer 8 under the control of signals from the outputs of the block 46 selectors. Read; from the OP information1 is entered into the b-register register 7 under the control of signals from the outputs of the selector unit 46. From the output 31 of the buffer register 7, information is received 1 at the information inputs of the OVC, and upon receipt of signals of sampling and recording, is recorded at the address set on the address counter 5 (output 22). After the information read from the OP in the buffer register 7, the counter 4 of the address is modified by the signal from the selector unit 46, and 1 is received from the OP at the following address followed by the record in the buffer register 7, then by the signal from the block 46 selectors, with output modifies the contents of the counter

5 addresses and in the OVC is recorded the second word read from the OP. Cycles reading OP - write OVC repeat until the contents of the counter 2 and

Q 5

0 5

Oh d

five

03

the formation producing the scaling down will not be zero. The signal 11 of the exchange from the output of the information counter 2 arrives at the input 14 of register 40, resets the request confirmation signal and, if the enable status of the state 3 register is set to a single logic level, generates an interrupt request signal.

By setting the request confirmation signal (output 17 of register 40) to the zero logic level of the one-one 41, the readiness of the registrar 3 state is set to a single level, and the start command bit is set to the zero logic level.

If, in register 3 of the state, the code of the read command of the OVC, the block 45 of the flip-flops, controlled by the corresponding clock outputs of the decoder, 44 generates the signals for sampling and writing the OA and sampling the OVC. Otherwise, the algorithm of the read instruction OCD coincides with the algorithm of the write command.

Claims (2)

1. A device for interfacing between a computer, an operative memory and an external storage device, containing a bidirectional switch, a buffer register, a status register, the first, second address counters, an information counter. The controls and the control unit, the first to the sixth outputs of the control unit, are connected respectively to the control input of the direction of transmission of the bi-directional switch, to the record input of the information counter, to the information input of the state register, to the summing inputs of the first, second address counters and to the syncro - the house of the buffer register, the first, second inputs of the control unit are connected respectively with the bit output of the information counter and with the output of the state register, the first information input / output bi-directionally The first switch, the information inputs / outputs of the first, second address counters, information counter and status register are the device input-output for connecting the computer information input-output, characterized in that, in order to increase the speed, an information multiplexer is entered into it and an address multiplexer, with the first, second information and control inputs of the address multiplexer being connected respectively to the input of the device for connecting the information input-output of the computer with the discharge output of the first network -; address block and with the seventh output of the control unit; the output of the address multiplexer is the output of the device for connecting the address memory input, the information output of the second address counter is the output of the device for connecting the address input of the external device, the eighth, ninth outputs of the control unit are the outputs of the device for connecting to the control inputs, respectively, of an external storage device and RAM, the information input of a bi-directional switch and the first information The input of the buffer register is the input of the device for connecting the information output of the main memory, the output of the buffer register is connected to the first information input of the multiplexer information and the output of the device for connecting the information input of the external storage device, the second information input of the buffer register is the input of the device for connecting the information external storage device output, information output of a bi-directional switch, co-dinene with the second The information input of the information multiplexer, the control input of which is connected to the tenth output of the control unit, the eleventh exponent of which is connected to the synchronous input of the status register, the output of the information multiplexer is connected to the output of the device for connecting the information memory input, the command input-output of the control unit device is the input-output device for connecting the information input-output of the computer, 1 2. The device according to claim 1, characterized in that the control unit comprises a receiver unit, a transmitter unit, a first, second, decoders, a block of AND-NES elements, a register of features, a command decoder, a block of OR elements, a register, a single vibrator , counter., block of triggers and block of selectors, moreover 0 five 0 five 0 five 0 five the input output of the unit is connected to input;) p; ohm of the NAND unit, with the first information input of the first decoder, with the output of the transmitter unit and with the input of the receiver unit, the first, second outputs of which are connected to the first information inputs of the register of attributes and the register, respectively , the first, second outputs of the block of elements AND-NOT are connected respectively to the second information input of the register of signs and to the second information input of the first decoder, the first to the fourth outputs of which are connected respectively from the first paragraph fourth inputs of unit OR element, a second data input of the register is a first input of a logic unit conditions, information Rin; :; the command decoder is the second input of the logic condition of the block, the first output of the register of attributes is the first output of the block, the first to the sixth outputs of the block of selectors are the second to the seventh outputs of the block, the first, second outputs of the block of triggers are the eighth, ninth outputs of the block The seventh output of the selector block is the tenth output of the block, the first to fourth outputs of the block of OR elements are the second to the fifth outputs of the block, the first output of the register is connected to the fifth input of the block of OR elements, with the first input The transmitter unit is the eleven unit output, the fifth output of the unit OR is connected through a serially connected one-shot and counter connected to the information input of the second decoder, the first to the sixth outputs of which are connected respectively to the first, second, third inputs of the trigger block, the second information inputs of the selector unit and the third information input of the register, the fourth information} the first input of which is connected to the sixth output of the block of the OR elements, the sixth input of which is connected with the first output of the command decoder, with the first control input of the selector unit and with the fourth input of the trigger block, the second output of the command decoder is connected to the seventh P input of the OR element block, with the second control input of the selector block and with the fifth input of the trigger block, second register output connected to the second 153110310 the input of the transmitter block, the second high output of the register of attributes, the connection of the register of attributes is connected to the ninth input of the block of elements by the eighth input of the block of the OR and OR elements and the seventh input of the trigger block to the sixth input of the trigger block, tracks.