SU1278869A1 - Interface for linking electronic computer with peripheral equipment - Google Patents

Abstract

The invention relates to the field of computing and can be used to build standardized devices for interfacing computers, for example, with external storage devices. The aim of the invention is to reduce hardware costs. The goal is achieved by the fact that the device containing the pulse generator, the And element, the counter, the delay element, the trigger, the decoder clock pulses, the first memory block, the first address decoder, the address register and two groups of switching elements, entered the receive register, the issue register , output register, group of multiplexers, group of meters, third group of switching elements, second address decoder, and second memory block. 1 il. (L with:

Description

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o The invention relates to computing and can be used to build unified computer interface devices, for example, with external memory devices. The purpose of the invention is. reduction of device hardware costs. The drawing shows the device block. The proposed device includes a clock pulse generator 1, element 2, counter 3, a decoder 4 clock pulses, a trigger 5, a delay element 6, a bus 7 a computer ready input, a bus for setting the initial conditions, and a switching bus 9 first and second groups, address register 12, first address decoder 13, first memory block 14: group multiplexers 15, output register 16, switching elements 17 of the third group, second address decoder 18, second memory block 19, counters 20 Py, reception register 21, issue register 22, tires 23 groups of outputs of external devices, bus 24 and 25 of the first and second groups of address outputs of a computer, bus 26 of output control of the NIN computer mode, bus 27 of the output of control of computer recording, bus 28 of a group of information outputs of a computer, tires 29 and 30 of groups of information inputs and outputs external device, bus 31 groups of information inputs of a computer, tires 32 groups of command outputs of external devices. The device works as follows. Switching elements 10, 11 and 17 are switched by a signal on bus 26, and block 14, depending on the value of this signal, operates in the mode of recording information or reading. Before starting the operation of the device, it is necessary to record information about the operation of the device in block 14, and in block 19, to write constants to control the counters 20 during operation. To do this, buses 26 and 9 are supplied with logical zero signals, as a result of which the device sets c to the recording mode, and the passage of pulses from generator 1 through element 2 to the input of counter 3 is prohibited. The signal on bus 8 causes trigger 5, counter 3, and register 16 to reset. Then, on record 27, a write enable signal is set, and on buses 8 and 9, a logical unit signal. In this case, the pulses from the generator 1 through the element AND 2 are fed to the input of the accountant 3, from where the number of counted pulses is fed to the decoder 4 in the parallel code. As a result, an impulse is received at the input of register 12, according to which the addressj specified on buses 24 and 25 is written to it. The address is decrypted by decoders 13 and 18, and in blocks 14 and 19 a cell is selected into which the information from the buses 28 is to be written. Counter 3 continues to count, and the signal from the decoder 4 sets the trigger 5 to one. In this case: information from busses 28 is recorded in blocks 14 and 19. Then the signal from decoder 4 sets the trigger 5 to its original state, which removes the signal for accessing blocks 14 and 19 and signals bus computer 7 to set new information and address . In this case, through the delay element 6, the counter 3 is reset to its initial state. Then the process is repeated several times until the necessary constants for controlling the counters 20 are written to blocks 14 and 19. Then the write enable signal is removed from the bus 27, allowing recording only in block 14. After this, the described process repeats again, the information on the operation of the device is recorded in block 14, and the information previously recorded in it is erased. At the end of the writing of the operation algorithm, a logic unit signal is sent to bus 26, allowing readout of information from b. 14, and switching elements 10, II and G7 switch the outputs of multiplexers 15 and corresponding groups of outputs of the register 16, respectively. Then a pulse signal is given logical zero on bus 8, drive counter 3, triger 3, and register 16 to the initial state. The process of reading information from blocks 14 and 19 is similar to the recording process and is controlled by generator 1,: 3, decoder 4, and trigger 5. The read addresses from block 14 are determined by the set of signals on mHftax 23, the outputs of counter transfers 20, and the corresponding Output register groups 16, readout addresses from block I9 are determined by signals at outputs of decoder 18, coming from multiplexers 15, which can switch any signal set to the inputs of switching elements 10. Output signals of block 1A are implemented The output functions of the control device. On the tines 23, the state signals of the external device, for example, the storage device (CDD), with which the computer operates (array markers, information sync signals, end contact signs, etc.) are sent. the outputs of register 16 issue commands to the OVC (movement of the carrier, stopping, writing, reading, strobe information, etc.). When writing information to the OVC, buses 28 are supplied from a computer to record information. The device generates a signal by which information is recorded in register 22. Then, at a certain moment, determined by one of the counters 20, the device detects the signal of the information output gate, which sends information to the buses 29 from the outputs of the register 22. When information is read out from the OVC, bused information appears on bus 30, and the accompanying clock signal triggers the release of a write signal to the register 21 from the device. Thereafter, information on bus 3 supplies the computer. When working with a one-bit storage medium (for example, a magnetic wire drive), the registers 21 and 22 are switched by signals from the inputs of the register 16 to the shift mode 45

information. Then, the recording information is output from the output of the register 22 bit, and the reception of information when it is received is made to the input of the low-order register 21. In this way, information can be repackaged at different computer word width and OVC width. The counters 20 are used to generate time stamps defining various commands, clock signals, information gates, and also monitoring time intervals in the OVC. Position

Claims (1)

switching elements, register. addresses, the first address deshifter and the first memory block, the outputs of the switching elements of the first and second groups are connected to the first and second groups of information inputs of the address register, the output group of which is connected via the first address decoder to the address input: the first memory block, whose sampling resolution input is connected to the trigger output, the third output of the clock decoder is connected to the control input of the address register. these time stamps are determined by the constants written to the corresponding counters from block 19. After writing the constant, counter 20 counts the specified number of pulses and outputs a transfer signal to the B51od of multiplexers 15, causing the device to issue a particular signal or fix the rate (non-norm) of the corresponding time interval , Commands to enter a constant in the counter 20 and the address to find the constants from block 19 come from the corresponding output output register groups 16. The fourth output output register group 16 and serves to produce the state functions completions device to combining those conditions devices in which analyzed small number of input variables. This saves device memory. Apparatus for interfacing a computer with external devices comprising a clock pulse generator, the output of which is connected to the first input of the element I, the output of which is connected to the clock input of the counter, the output group of which is connected to the group of inputs of the depressor sync pulse, the first and second outputs of which are connected with the installation and counting inputs of the trigger, the second output of the depigurator of clock pulses is connected to the first reset input of the counter and the readiness of the computer via a delay element, the second reset input the trigger and the reset input, the trigger is connected to the output of setting the initial conditions of the computer, the second input of the element I is connected to the output of the start of operation of the computer, two groups of computers, in order to reduce hardware costs, a group of multiplexers, an output register, and a third group are entered into it switching elements, the second address decoder, the second memory block, a group of counters, the receive register and the issue register, the output of the first memory block connected to the information input of the output register, the reset input of which is connected to the reset output of the EV M, and the synchronous input - with the fourth output of the decoder of clock pulses and counting inputs, group counters, whose transfer outputs are connected to the first groups of information inputs of group multiplexers, the second groups of information inputs of which are connected to the group of external state outputs, devices, first information inputs of the first switching elements and the second groups are connected respectively to the first and second groups of address outputs of the computer, the second information inputs of the switching elements of the first group are connected to the outputs and multiplexers of the group, the write-read-out of the first memory block and the control unit inputs of the switching elements of the first, second and third groups are connected to the computer mode control bus; the first and second information inputs of the switching elements of the third group are connected respectively to the output register group of the address register and the first group of outputs of the output register, the outputs of the switching elements of the third group are connected through the second decoder addresses with the address input of the second memory block, the write / read input of which is connected to the write control output of the computer, and the enable input the samples - with the trigger output, the information inputs of the first and second memory blocks are connected to the group of information inputs of the output register and the group of information outputs The computer, the group of information inputs of external devices are connected. To the group of outputs of the output register, the clock input and the shift control input of which are connected respectively to tepBbiM and the second bit outputs of the 5 OUTPUT register, the second group of bit outputs of which is connected to the counters resolution enable inputs of the group, information inputs which are connected to the output of the second memory block, a group of information inputs of a computer and information outputs of external devices are connected respectively to a group of outputs and the information input of the reception register, the synchronous input and the control input, the shift of which is connected respectively to the third and third outputs of the output register, the third group of outputs of which is connected to the group of command inputs of external devices, and the fourth and rtataa groups of outputs of the output register are connected respectively to the third information groups of inputs and the control inputs of the group multiplexers, the pole, the output register group of the output register is connected to the second information inputs of the switching elements of the first Rupp.