SU1661781A1 - Device for interfacing processors in distributed computing system - Google Patents

Abstract

The invention relates to computing and can be used to create computer networks. The aim of the invention is to improve the performance of the system by combining the processes of writing data to the interface device and transmitting it over communication channels. The goal is achieved by the fact that in a device containing a memory block 1, a write address counter 2, a rewrite address counter 3, a reversible counter 4, groups 5, 6, 8 AND elements, a group 7 OR elements, triggers 9, 10, elements 11, 12, delay elements 13, 24, elements OR 14, 25, element 15 and 15, the second memory block 16, read address counter 17, second reversible counter 18, groups 19, 20, 27, elements And the second group 21 elements OR , two triggers 22, 23. 1 Il.

Description

The invention relates to computing and can be used to create computer networks.

The purpose of the invention is to improve the system performance by combining the processes of recording data into the interface device and transmitting it over communication channels.

The drawing shows a block diagram of the proposed device.

The device contains a memory block 1, a write address counter 2, a rewrite address counter 3, a reversible counter 4, groups 5 and 6 elements AND, a group 7 elements OR, a group 8 elements AND, triggers 9 and 10, elements 11 and 12 delays, elements NOT 13, OR 14, And 15, memory block 16, read address counter 17, reversible counter 18, groups 19 and 20 elements AND, group 21 elements OR, triggers 22 and 23, element NOT 24, element OR 25, element 26 delays, a group of 27 elements And, information 28, address 29, write control 30 and read 31 inputs of the first memory block, information output 32 of the first memory block, information 33, address 34, read control 35 and write 36 inputs of the second memory block, information output 37 of the second memory block, data read signal input 38, data input / output 39, data write signal input 40 , input-41 readout of the state of the first memory block, input 42 of the signal reset, output of the data-recording inhibit signal 43, input 44 of clock pulses, data output 45, input 46 of the state readout of the second memory block, output 47 of the signal-read-out device data .

The device works as follows.

In the initial state, the counters 2, 3, 4, 17 and 18 are in the zero state, the output of the trigger 9 is removed, the signal O, indicating the absence of data in the first memory block 1, the output of the trigger 22 is removed, the signal 1, allowing overwriting data in the second memory block 16, at address 29 of the first memory block 1 and address input 34 of the second memory block 16 there is a potential O, which corresponds to the counter 3 address of the rewriting address, at information output 37 of the second memory block, the output of elements And groups of 8 and the outputs of elements And groups s 27 a high resistance condition is maintained, at the output 43 of the data recording prohibition there is a potential of the enabling signal, at the output 47 of the read prohibition signal the potential of the inhibiting signal is maintained, the output of the write and read addresses from counters 2 and 17 through

elements OR 7 and OR 21 are blocked at address inputs 29 and 34 by AND elements of groups 5 and 19, the second control inputs of which receive zero potentials of write and read control signals from inputs 38 and 40 of the device.

The process of writing data reads to the device begins with an analysis of the devices that read the device or

0 by the recording processor of the state of the write prohibit signal output 43 or the read prohibit exit 47. In the absence of prohibitive signals at outputs 43 and 47, the recording and reading

5, the processors may read the state of the reversible counter 4 of the fill level of the first memory block 1 and the state of the reversible counter 18 of the fill level of the second memory block 16, respectively.

0 The reading of the status of counters 4 and 18 can be done simultaneously.

In the initial state, only writing data to the device is permitted. The recording processor puts the data on

5 input-output 39 of data and generates a Write command at input 40, which sets trigger 9 to one state, by its inverse value from the element EE 13 blocks blocking the address of zero zero from output of counter 3 of rewriting through AND elements of group 6 and elements OR groups 7 to the address input 29 of the first memory block, permitting the zero address to be fed to this input from the counter 2 for recording data through AND 5 and OR 7 elements, and generating at the output of the delay element 11 a signal that controls writing data to zero cell block 1 memory Ti. Data is being written to memory block 1,

0 after which the recording processor removes the recording control signal from input 40. The trailing edge of this signal is the transfer of the states of the recording counter 2 and the reversing counter 4 to the following

5 states, i.e. the number stored in them is increased by +1.

Removing the recording signal from input 40 again blocks the output of the write address to input 29 of the first memory block from the output of counter 2

0 through the elements AND 5 and OR 7 and outputs to the input 29 the address of the zero cell for rewriting from the counter 3 rewriting through the elements AND b and OR 7. At the same time, the address of the zero cell from the counter 3 rewriting is fed through the elements AND group 20, to the second inputs which receives the enable signal 1 from the output of the element NOT 24, which corresponds to the absence of a read control signal from the device at input 38, and through the elements OR to the second

Groups 21 are not address input 34 of the second memory block 16. The output of the read address from counter 17 is blocked by the signal O at the inputs of elements AND of group 19. At all inputs of element 15, except for the input of the clock signal from input 44, signals 1 are sent. The device is prepared for rewriting the information word from memory 1 in memory block 16, which occurs with the arrival of a value of 1 clock pulse.

With the occurrence of the value of 1 clock pulse at the output of the element 15, a single signal is generated, which is fed through the delay element 12 to the input 31 of the read control of the first memory block 1 and the write control input 36 of the second memory block 16 and overwrites the contents of the zero cell of the block 1 memory in the zero cell of the memory block 16, the trailing edge of the signal from the element 15 after the arrival of the level O of the signal of the clock pulse 44 translates the state of the counter 3 rewriting into the following: corresponding to the first address chey- ki memory value of the first down counter 4 returns to the previous - zero and its output signal sets the flip-flop 9 to null state, and the ON signal output from the flip-flop 9 blocks the AND gate 15 at the next clock transition. The falling edge of the signal from AND 15 also transfers the second reversible counter 18 to the next state and sets the trigger 23 to a state in which a signal with a potential allowing data reading is received from its output to the device output 47. The write and rewrite cycle ends there. In the future, in the absence of reading data from the device, the write and rewrite cycles will occur in a sequence similar to that discussed earlier, until the second memory block 16 is completely filled, which is detected by the overflow of the reversible counter 18 and the appearance at its output of a signal which sets trigger 22 to the zero state. The zero signal from the output of the trigger 22 blocks the further development of the control overwriting signals from the AND element 15 and the overwriting of the data from the recording unit 1 to the memory unit 16 is stopped.

After the last free cell of the first memory block 1 is filled, the first reversing counter 4 overflows and a single signal appears at its output, which sets the second trigger 10 to the state corresponding to the output of the output 43 of the prohibition of writing data to the device. From this point on, the device is closed for recording data and is in the standby state of the read mode. The removal of the write inhibit signal from output 43 is ON while performing a read cycle and an overwrite or arrival of the reset signal 42.

The read cycle of the data from the device begins with an analysis of the state of the read inhibit signal 47 and the analysis of the filling level of the second memory block 16, which is reflected by the state of the reversible counter 18. The operation of the device in the data output mode to the reading processor is performed when there are no data writing cycles in the device and the state of complete filling of the device with data.

After analyzing the state of the signal at the output 47, the read control input is sent to the read input 38, which enables the connection of the address of the first cell to be read, stored on the counter of the read address 17, through elements 19 and OR 21 to address 34 of the second memory block 16 and locks the rewrite address from counter 3 on the AND elements 20. The read signal 38 is supplied through the delay element 26 to the read control input 35 of the second memory block 16 after the read address 34 has been set, and at the output 37 of the second memory block 16 The contents of the addressable memory cell, which is fed to the output 45 of the device data and is read by the requesting processor. The removal of the read signal -38 causes the reversing counter 18 to go to the previous state (the number stored in it is reduced by 1} and the trigger 22 is set to one state through the OR element 25, at which T from its output is fed to the input element I 15. At the other inputs of the element 15 there are also single signals which indicate the absence of a device access cycle at the given moment and the presence of data in the first memory block 1, which is confirmed by a single signal at the output of the trigger 9.

The arrival at input 44 of a single clock pulse signal causes the occurrence of G at the output of element 15, which is fed through a delay line 12 to the read control input 31 of the first memory block 1 and the write control input 36 of the second memory block 16, at address inputs 29 and 34 of which there is a read and write address from counter 3. The information word is overwritten from memory block 1 to the thief by memory block 16. The arrival of a zero clock pulse removes a single signal from the output of element 15, causing the rewrite counter 3 to go to the next address, decreasing the value of the reversing counter 4 by 1, setting trigger 10 to a state at which recording potential is output to output 43 reversible counter 18 to the next state and issuing an overflow signal from its output, which sets the trigger 22 to the zero state and O from its output blocks through element 15 further rewriting of data. The process of rewriting data after reading data from the device is similar to the process of rewriting after writing data to the device.

After the end of the data reading cycle from the device accompanying the rewriting process, one memory cell is freed in memory block 1, the second memory block 16 remains completely full. Further sequential output of data from the device without writing to it first leads to the output of all information from memory block 1, resetting the reversible counter 4 and setting trigger 9 to the zero state, which blocks the further rewriting. Then, the data from the second memory block 16 is sequentially outputted, and with the contents of its last memory location displayed, the contents of the reversible memory counter 18 becomes zero, and the signal from its output sets the trigger 23 to a state corresponding to outputting the output 47 to the output 47 further reading data from the device.

In the mode of simultaneous access of the writing and reading processors; the device operates as follows.

After analyzing the state of the permissive signals at outputs 43 and 47, the writing processor places data on bus 39 and produces a write signal 40, and the reading processor produces a read signal 38, after which data is written to the first memory block 1 and reads data from block 16 memory in the specified sequence. The temporal overlap of the write and read signals within one clock cycle can be arbitrary. The data rewriting process will be blocked until the last control signal is removed, with the same duration of these signals. Since the data entry in the RAM

processor or data output from the processor to the device always requires a few machine cycles, during the majority of which the device is in the state

waiting, and the rewriting process is carried out in one working cycle, then even if the array elements are sent sequentially, several rewriting processes will occur within the device. Implementation of data rewriting into the device during the course of data input or output cycles. those. embedding the rewriting process in a time cycle of clock cycles to record or

reading data by processors, and parallel execution of these operations realizes the possibility of simultaneous work with the device writing and reading processors, eliminating their downtime during

access to the device.

Claims (1)

The invention includes a device for interfacing processors into a distributed computing system containing a memory block, a write address counter, an overwrite address counter, a reversible counter, three groups of AND elements, a group of OR elements, two triggers, two delay elements, and a signal input the device data record is connected to the first inputs of the AND elements of the first group, with the counting input of the write address counter, with the forward counting input of the reversing counter, the input of the first delay element and the reset input of the first trigger, the outputs of the AND elements of the first group are connected to the first inputs of the OR elements of the group, the outputs of which are connected to the input of the address of the memory block, the information output of the write address counter is bitwise connected to the second inputs of the AND elements of the first group, the outputs of the AND elements of the second group are connected to the second inputs rows or groups of elements, the input signal block read state memory device coupled to the first inputs of AND gates of the third group, the outputs of which are connected bitwise with the data input unit and the memory are input-output device data, the information output of the reversible counter is bitwise connected to the second inputs of elements AND of the third group, the forward overflow output of the reversible counter is connected to the installation input of the first trigger, the inverse output of the overflowing reversal counter is connected to the installation input of the second trigger, the direct output of which is the output signal prohibition of recording device data, the output of the first element The delay is connected to the memory control input of the memory block, characterized in that, in order to improve the system performance by combining the processes of writing data to the interface device and transmitting it over communication channels, a second memory block, a reversible counter, a group of elements are introduced into it. OR, three groups of AND elements, two triggers, two NOT elements, a third delay element, a read address counter, two OR elements. the AND element, and the device reset input is connected to the first inputs of the first and second OR elements, the output of the first OR element is connected to the reset input of the second trigger, the output of the second OR element is connected to the installation input of the third trigger, the reset input of which is connected to the forward overflow output of the second reversing a counter whose forward counting input is connected to the second input of the second element OR, to the counting input of the read address counter, to the first inputs of the AND elements of the fourth group, the input of the first element NOT, the input The third delay element is the input signal of the device reading data, the reverse count input of the first reversible counter is connected to the count input of the rewriting address counter, with the second input of the first OR element, with the reverse count input of the second reversing counter, reset input of the second trigger, input The second delay element and the output of the element And, the first input of which is connected to the output of the second element NOT and the first inputs of the elements And of the second group, the second inputs of which are bitwise connected to the information the output of the address counter rewriting and the first inputs of elements And the fifth group, the outputs of which are connected to the first inputs of the elements OR of the second group, the outputs of which are bitwise connected to the address input of the second memory block, the second input of the AND element connected to the output of the first trigger, the input clock of the device, the fourth input element And is connected to the output of the first element NOT and the second inputs of the elements And the fifth group, the fifth input of the element And connected to the output of the third trigger, information output reversing The bit cell is connected to the first inputs of the elements of the sixth group, the second inputs of which are connected to the read input of the state of the second memory block of the device, the outputs of the elements of the sixth group are connected to the information output of the second memory block, and The second delay element is connected to the read input of the first memory block and the write input of the second memory block, the read input of which is connected to the output of the third delay element, the information output of the first block pa These are connected to the information input of the second memory block, the information output of the readout counter is bitwise connected to the second inputs of elements AND of the fourth group, the outputs of which are connected respectively to the second inputs of the OR elements of the second group, the inverse overflow output of the second reversible counter, connected to the installation input of the fourth trigger, the output of which is the output of prohibiting the reading of the device.