SU1401465A1 - Memory control device - Google Patents

Abstract

The invention relates to computing and can be used in hardware and hybrid monitors to record the course of programs. The aim of the invention is to increase speed. Dp this in the mouth. An array containing two registers, a memory block, three counters, an OR element, two AND elements, four registers additionally are added, a pulse driver, four AND elements, a shift register, a multiplexer. The device does not require for the time of reading the write lock information. The word-by-word reading of information from the memory block is performed in pauses between write cycles. 1 il.

Description

4 O5 O1

The invention relates to computing and can be used in hardware and hybrid monitors to record the course of programs.

The aim of the invention is to increase speed.

On the drawing is a diagram of the device.

The device contains -input 1 record recording, trigger 2, element OR 3, trigger 4, information input 5, register 6, element 7, shift register 8, trigger 9, multiplexer 10, counter 11, memory block 12, and elements 13 and 14, pulse shaper 15, elements AND 16 and 17, read resolution input 18, trigger 19, AND element 20, counter 21, counter 22, register 23, information output 24, read sign output 25, output

26 error indication, clock input 27.

The device works as follows. -.

In the initial state, all the triggers (except trigger 9), counters and registers are reset to O, trigger 9 is set to 1.

Simultaneously with the information on the course of the program being debugged, a signal arrives at the input 1 of the recording resolution, which is transmitted to the input of the setup in 1 trigger 2 and cocks it. As a result, the logic level 1 formed at the output of flip-flop 2 is fed to the first input of the element OR 3. At the same time, the same potential is fed to the information input of flip-flop 4.

The information about the progress of the program being debugged, arriving at the information input of the device 5, is then fed to the information inputs of the register 6. Recording to the register 6 is performed by a signal received from the input 1 of the device to the input of the resolution of the recording of record 6.

A single signal from the output of the element OR 3 is fed to the first input of the element AND 7, the second input of which receives the clock pulses from the input

27 devices.

Thus, while the trigger 2 is set to one, the clock pulses constantly pass to the output of the And 7 element, which then goes to the synchronization input of the shift register 8

The first clock pulse is written B to the first register bit B 1, arriving at the input of the register 8 shift control from the trigger output 9. A single signal from the first register bit 8 output is fed to the setup input at the O flip-flop 9 and to the sync trigger input 4. At This appears on the trigger 9, O, and on the forward output of the trigger 4 1, which, arriving at the control input of the multiplexer 10, allows information from counter 11 to pass through it. The resulting binary code at the output of the multiplexer 10, arrives on addr waist section 12 inputs the memory, thereby determining the address of the cell in which information is recorded.

The second clock pulse shifts 1 to the second bit of register 8, and to the first bit writes O, coming to the input of the shift register control 8 from the trigger 9. The single signal from the output of the second bit of the register 8 goes to the second inputs of the And 13 and 14 elements , the first inputs of which are connected respectively to the direct and inverse outputs of the trigger 4.

As a result, a single signal at the output of the element And 13 is fed to the input of the recording resolution of the memory block. This signal records the progress of the monitored program from register 6 to the zero cell (contained in the initial state zeroed by counter 11) of memory block 12.

The third clock pulse shifts 1 to the third digit of register 8, and in the second digit it records O in a similar way.

A single signal from the output of the third bit of register 8 is fed to the input of the pulse former 15. Formed as a result, at the output of the element 15, a signal of a certain duration arrives at the second inputs of the elements 16 and 17, the first inputs of which are connected to the direct and inverse outputs of the trigger 4, respectively.

At the same time, the signal from the output of the pulse shaper 15 is fed to the input of the setup in 1 trigger 9 and shift register 8. As a result of re 1401465

The trigger 8 is zeroed out, and the trigger 9 is set at the output of the element 17 and is completed, it is poured into a single state. recording information into register 23, at the output of the element AND 16 of the rag- ing, the course of which is connected to the information signal of a single signal, which, when inputting the counted input of the counter 11, increases its content by one, thus the memory block is redirected.

At the same time, the pulse from the output of the element's output of the element And 17 simultaneously of the instruction And 16 arrives at the input of the set- comes at the output of the readout sign in O of the flip-flop 2 and resets it, the device and the input of the installation as a result, the register 8 is blocked.

The process of reading information from the memory block starts from the time of the 15 cells of the memory block 12. From the output of the input on input 18 of the signal of the AND 16 when recording into a cell or with

the output element And 17 when read, the generated pulses are supplied to the sleepy output 24 of the device.

The memory block is redirected by the pulse generated on. the output element And 17 and arriving at the input +1 of the counter 22. The signal from

in About trigger 19, dropping it. Counter 21 determines fill

Do not count the shanni that enters the input of the setup in 1 trigger 19 and cocks it. The signal generated at the output of the trigger 19, receives 20 counter 21, changing its contents. On the first input of the element I 20, on the second In the case of filling all the cells, respectively, on the inputs of FH or -1

Pitel (counter overflow 21) signal Error from the overflow output is output to output 26 of the sign 25 of the device error.

A swarm whose input gets a signal from the output of counter 21.

The signal at the output of the AND element 20 appears only if at least one cell is filled in the memory block.

The signal from the output element And 20 enters the input element OR 3. Formed as a result, the output element OR 3 single signal received at the first input element And 7, allows the passage through it of the clock frequency supplied to the second input element And 7.

Similar to the write process, the shift register starts and operates.

Upon arrival at the synchronization input of the trigger 4, a single signal from the first output of the first bit of the shift register 8, at the forward output of the trigger 4 is established. O, on the inverse - 1. As a result, at the control input of the multiplexer 10 there is a control signal that allows the code 22 to pass to the address inputs of the block 12 of memory.

At the next time point after the formation of a single pulse at the output of the second bit of the shift register, at the output of element I 14 a single signal is produced, which is connected to the information signal

24 output device.

The memory block is redirected by the pulse generated on. the output element And 17 and arriving at the input +1 of the counter 22. The signal from

the output of the element And 17 at the same time goes to the output of the sign of reading the device and to the input of the installation

cells of memory block 12. From the output of the element And 16 when writing to a cell or with

in About trigger 19, dropping it. Counter 21 determines fill

counter 21, change its contents. In the case of filling all the cells in response to the inputs of the FH or -1

0 counter 21, changing its contents. In the case of filling all the accumulator cells (counter overflow 21) the signal Error from the overflow output is sent to the output 26 of the sign 5 of the device error.

Claims (1)

Invention Formula A memory control unit containing two registers, three counters, a memory block, two AND elements, an OR element, the information inputs of the first register being information inputs of the device, the output of the first register connected to the information input of the memory block, information output which is connected to the information input of the second register, the output of which is the information output of the device, which is different in that, in order to increase speed, four triggers from the third to the sixth elements are entered into it And, shift register - multiplexer, driver 5 pulses, the inputs of the first and second flip-flop inputs are respectively the write enable input and the read enable input of the device, the output of the first flip-flop is connected to the first input of the OR element and the information input of the third flip-flop, the output of the second flip-flop is connected to the first input of the first And element, the output of which is connected 0 The second reads the information gg with the second input of the OR element, the output from the memory block 12. The read one is connected to the first input of the formation and is fed to the information element of the second element, And the input of the register 23. According to the signal that comes to the input of the record of the register 23 the second element And, the second input of which is the clock input of the device, the output of the second element with the second input element OR, the output of which is connected to the first input of the second element AND, the second element And, the second input of which is the clock input of the device, the output of the second element of resolution by the multiplexer input, the first and second, the input of the recording permission by the device whose information inputs are connected to the outputs of the first and second te.stvo connected to the entry of the first register. permission, entry entry permission is connected to the first register entry entry.