SU1529208A1 - Information input device - Google Patents

Abstract

The invention relates to computing, in particular, to devices for inputting digital-analogue and functional information into a computer, and can be used in data entry consoles and automated control systems. The aim of the invention is to increase the reliability of the input information by controlling the fact of the information entering the digital computer and its visual display. The device contains a keyboard 1, a group of display elements 3, the first 5 and the second 18 decoders, the switch 6, the pulse generator 7, the And 8 element, the first 9 and second 15 counters, the first 10 and second 17 blocks of RAM, three registers 11,19 , 20, comparison unit 12, trigger 14, first 13 and second 16 pulse shapers, first 21 and second 22 groups of amplifiers. With appropriate execution of the elements of the display, it is possible to provide information from the digital help information for the operator and thereby the organization of a dialogue between the operator and the digital computer. 4 il.

Description

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The invention relates to computing, in particular, to devices for inputting alphanumeric and functional information to a computer, and can be used in data entry consoles in an automated control system.

The aim of the invention is to increase the reliability of the input information by controlling the fact of the information entering the digital computer and its visual display.

Tsa FIG. 1 shows the functionality of the device; in fig. 2 is a comparison block diagram; in fig. 3 is a diagram of a first pulse generator; FIG. 4 is a diagram of the second pulse driver.

The device contains a keyboard 1, a group of keys 2, a group of elements 3 of one-sided conduction, elements 4 of the display, first decoder 5, switch 6, pulse generator 7, element C 8, first counter 9, first block 10 of the operative memory, first register 11 , comparison unit i2, first shaper 13 named after coEi, trigger 14, second counter 15, second shaper 16 pulses, second operative block 17, second decoder 18, second 19 and third 20 registers, first 21 and second 22 rpynni i amplifiers, .two trig- I epa 23 addresses, switch 24 records in OZK, ale m C 25, trigger 26 controlled the Theoretical pei HCTpOM 1 January reception and transmission, reception and transmission switch 27, a shift counter 28, TSLI member 29, triggers 30, 31, AND gate 32.

The device works as follows.

Generator 7 pulses through the element And 8 starts the counter 9, m of the younger bits of which are fed to the inputs of the decoder 5, and n high-order bits to the address inputs of the switch 6. According to the code from the counter 9 den.1 the digester 5 The 1T5 classbus bus of class 1, of the rest, on the remaining, which at this time the signals “1. If key 2 is closed, the “O” signal will pass to the input of switch 6. The signal from the switch output, b, is written as “b” at the address corresponding to the code of this keyboard key 1 to the first RAM of the main memory unit.

Comparison unit 12 is designed to be protected from the chatter of key 2 by comparing the code received from the output of switch 6 with the code received from the output of the first block 10 of operational information during a certain time interval. The operation of the comparison unit is as follows. The digital pulse from the commutator 6 is fed to the inputs of the multiplexer 24. The state of the address inputs. The multiplexer 24 forms the recording sequence of the signal 1 from the switch 6 in RAM 1 and RAM 2 of the memory block 10. The operation of the first memory block 10 is constructed so that first

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information is read at the selected address and then recorded. The information read from the RAM and RAM 2 is fed to the input of the flip-flops 23, which fix it and form the address for the address inputs of the multiplexer 24. This address is written "1 or" O to a specific RAM. In the first survey, a read is made from RAM 1 and RAM 2 before its state i and key (zeros were written to both RAMs beforehand). The read information is recorded in triggers 23. However, the set address is recorded as "1 in RAM f and" in RAM 2. At the second interrogation, code 10 is set at the address inputs of multiplexer 24,: which records "O in RAM I in RAM 2 During the third survey, when reading information from RAM 1, RAM 2, and writing to the address 23 triggers of multiplexer 24, the "1 to RAM 1 and RAM 2" is written. During the fourth and subsequent readings of the key code, the "1" is recorded and RAM 2, and thus the state of "1 key pressed is stored in the first block 10 RAM.

At the output of the element 25 after the third survey, a pulse is written to write the code of the pressed key c) Registry 11, which enters block 13 and installs trigger 14, which enables the pulse train to pass to the first counter 2. At the same time, this signal is output to the device as Signal "Ready.

The information in pei HCTpe 1 1 is stored until the request signal for input of the first driver of 13 pulses comes from the digital computer. The trigger 26 generates the address of the switch 27 in such a way that the clock frequency is received from the generator 7 pulses through the switch 27 and the element OR 29 on the counting input pei ncTpa AND, realizing the shift of the sequential code of the pressed key in the digital computer. On the output of the device, impulses with a frequency of shear arrive. Counter 28 is used to count the number of shift cycles. The overflow pulse of this counter sets to the initial state the trigger 26 of the first pulse shaper and the trigger 14 of the mode. The processed information in the digital computer is indicated by the signal "Input arriving at the input of block 13. This signal triggers 26 form the address of the switch 27 in such a way that a serial code with a shift frequency from the digital computer is received into the register I. The overflow pulse of the counter 28 sets to the initial state of the trigger 26, in the O generator 7 pulses, generating control signals for the counter 15, the second memory block 17, the second driver 16 pulses and the register 19. The information from the register 11 is rewritten into the counter 15 and in the second pulse shaper.

The information word C of the register II contains the address of the display element and the control bits "Input," Ignite, "Redeem. The control signals from the pulse generator 7 rewrite the state of the flip-flops 30 and 3 of the block 16 into the second memory block 17 at the address indicated.

In order to obtain a sufficiently bright luminescence of the display element, information from the second block 17 of the operational block is bit-wise entered into the register 19, and then rewritten in parallel by the overflow pulse P1 of the lower bits of the counter 15 into the register 20 serving for the line-by-line storage of the states of the display elements in the process of this line. The older bits of the counter 15 are fed to the input of the decipheror 18, which organizes the selection of the necessary groups of display elements. The groups of amplifiers 21 and 22 feed the required elements of the display 4 in the row and column. Thus, the key pressed (key) is illuminated when the corresponding information comes from CB.M. This is a control of the flow of information into the digital computer, which increases the accuracy of its input. The highlight of any display element occurs by the command “Input from a Digital Computer.

Claims (1)

Invention Formula A device for entering information containing a keyboard, a generator and pulses, a comparison unit, the first register, the first operational parameter block, the switch, the first decoder, the first counter, whose outputs are connected to the information inputs of the first decoder and the first register, addressable the inputs of the first memory block and the switch, the information inputs of which are connected to the outputs of the keyboard, the inputs of which are connected to the outputs of the first decoder, the output of the switch room is connected to the first input of the comparison unit, the second the stroke of which is connected to the output of the first memory block, whose information input is connected to the second output of the block 0 the comparison, the clock input of which is connected to the first output of the generator and pulses, the output of the register is the information output of the device, characterized in that. that, in order to increase the reliability of the input information, pulse shapers, trigger, element I, second counter, second memory unit, second and third registers, first and second groups of amplifiers, second rarator, group of display elements whose cathodes are entered into the device connected to the outputs of the first; groups of amplifiers, the inputs of which are connected to the outputs of the third register, the formation inputs of which are connected to 5 outputs of the second register, information inputs of KOTOpoi o are connected to the outputs of the second RAM block, the information inputs of which are connected to the outputs of the second imaging unit, and the address inputs are connected to the outputs 0 of the second counter and the inputs of the second descrambler, the outputs of which are connected to the inputs of the second group of amplifiers, 1, the outputs of which are connected to the anodes c), 1, display elements, the clock input of the third The 5th register is connected to the overflow output of the second counter, the information inputs of which are connected to the output group of the first register and to the information inputs of the second importer, 1sec, the control input, the shadow of which is connected to the installation input of the second counter, the first output of the first impulse generator trigger and control m input pulse generator, the first output of which is connected to the clock inputs of the first operational unit 5 pa.mti, second register of the second b, 1 operative rate; ti, the second counter, the second pulse driver, and the second output is connected to the first output of the first imp driver, ths and the first A input, whose output is connected to a clock input of the first counter, and a second input to a control input of the first register and a output of a three-liter, the second installation input of which is connected to the second input of the first form of the pulse body The second output of the comparison unit is the device ready output, the clock input of the first register is connected to the second output of the first pulse shaper, the third output of which is the clock output of the device, and the group of inputs is the device's rpynnoi inputs. From 1 Gotog Oslp & S DVM, p, u From ({/ jy /; YU From 7 it 23 From (um) g YU t From to om t a torus and b Code from If SH 0 / p P W t p K ( YU l 5 2 JAM2L W 2 with . g and lane Shif maifrnoS i s  ft) EX r s 00 Physical.ch