SU1003145A1 - Buffer storage device - Google Patents

Description

The invention relates to digital computing and can be used in the equipment for transmitting discrete information and in computer technology for interfacing devices. Known Bus Memory Storage Device), which contains data registers, write registers to registers and control circuits. Records to registers made on the basis of triggers and coincidence elements, in which data is written to the memory and overwrites data inside the memory in pulses. produced by a clocked control circuit tl 1. A disadvantage of this device is the need for an external source of clock pulses, as well as the complexity of the circuit design due to the large number of elements. In addition, in these devices, there is a distortion of the read information during asynchronous operation connected to the buffer memory. The closest in technical essence to the present invention is a buffer storage type, containing a number of code registers connected in series with each bit, a write signal bus, a number write control signal, a rejection signal, a write erase signal, a number control signal and tires for building up the device, with the information inputs of the first register connected to the information inputs, and the information outputs of the last code register to the outputs of the buffer memory. Each register has a control circuit executed on the NAND element and the trigger, the single input of which is connected to the control inputs of the given register and the input of the given NAND element, the zero input of the trigger is connected to the output of the same NAND element, To the other three inputs of the element | AND-NOT connected as a single pig. the course of a given trigger, the zero output of a subsequent trigger, and the output of a subsequent AND-NOT element. The control inputs of the first register are connected to the write bus. The zero output of the trigger in the control circuit of the first register is connected to the number record control bus, the output of the NAND element, at the same time as the control of the last 1 register, is connected to the control signal bus of the number 23. information in the storage device before the signal ends; The purpose of the invention is to increase the speed of the device. This goal is achieved by the fact that in the buffer memory devices containing sequentially connected registers, the inputs of the first of which are information inputs of the device, the outputs of each of. The registers are connected to the information inputs of the subsequent register, and the outputs of the last register are the information outputs of the device connected in series through the elements. IS-NOT triggers, the first output of each of which is connected to the first input of the corresponding element AND-NOT the output of each of the IS-NOT elements is connected to the first input of the next trigger, to the control input of the corresponding register, to the first input n of the following I-element NOT, to the second input of the previous trigger and to the second. Input of the previous NAND element, the first output of each trigger is connected to the third input of the subsequent NAND element, the second output of each trigger, except the last, is connected to the fourth input of the previous element This NAND, the first and second inputs and the second output of the first trigger, the second and fourth inputs and output of the last element AND are NOT the corresponding control inputs and outputs of the device, an additional trigger and the element AND-OR-NOT, the first input are entered which is connected to the output of the additional trigger, the first input of the additional trigger is connected to the second output of the last trigger. the second trigger input is connected to the second and third inputs of the element AND-ILINE and is the corresponding control input of the device, the fourth input of the AND-OR-NOT element is connected to the output of the last AND-NOT element, the output of the AND-OR-NOT element is connected to the second input the last trigger and to the second input of the previous NAND element. The speed of the device increases as a result of reading new information from the buffer storage device to the last register before the end of the signal to erase the record in it, and the additional trigger with the AND-OR scheme does not preserve the information recorded in the last register of the device. The drawing shows a functional diagram of the proposed buffer memory. The device contains registers, each of which is executed on triggers, triggers 3 control registers, elements. AND-NOT, additional trigger 5, element AND-OR-NOT 6, control output 7 of the record number, control input 8 of the record, information inputs of the device 9- | -9f, control input 10. reset, control input 11 of the signal erase recordings, control inputs 12 -14 for increasing the device, controlling the output 15 of the signal, controlling the presence of the number, informational outputs of the device. The device works as follows. When a write signal arrives at the input 8 of the record in the first register 1, information is recorded, at the same time the trigger 3 of the control circuit of the first register is activated and the signal from its single output unlocks the first AND-NOT element k. The signal, which appeared at the output of the first AND-HE k element, allows overwriting of information in the second register 2, to the same, the second trigger 3 is triggered, the first trigger 2 is reset and the second AND-HE element k is locked. The signals at the unit output of the first flip-flop 2 and at the zero output of the second flip-flop block the first AND-NO element 4 and the information rewriting signal in the second register 1 ends, and the second AND-HE element k is unlocked. the signal at the output of which allows the information to be overwritten in the third register 1-J. Thus, the sequential shift of information received in the storage device to the register, the AND-HE element k of the control circuit of which is blocked by the signal from the zero output of the three | control the next register. After the signal overwrites the information into the last register If, and if there are signals at inputs 12 and 13, the trigger of the control circuit of the last register returns to its initial state by the signal from the output of the AND-OR-NOT element 6, the inverse of which receives a signal from the output element AND-NOT 4. -After reading the information from the last code register, a signal is sent to the write erase input 11, which blocks the second valve and opens the first valve of the AND-OR-H 6 element and enters the additional input unit 5 ggera reset circuit, leaving it in the original state. The signal from the output of the element. AND-OR-NOT returns the trigger of the last control circuit to the IS ;; one state and blocks the penultimate element of the IS-HE t; the signal from the zero output of the trigger 3 trips the trigger of the reset circuit to the single state, thereby blocking the first gate of the element AND-OR-NOT 6, and delivers the enabling signal to the first input of the penultimate last element AND-NOT. The signal at the output of the AND-OR-NOT 6 element ends by unlocking the element AND THE NOT control circuit of the penultimate register if the trigger of the previous control circuit is in the unit state, i.e. the register contains a number, after the output of this element, AND-NOT 4, the signal permits the overwriting of information into the last register and is set. the trigger of the control circuit of the last register to one state; otherwise, no rewrite is performed.

At the same time, the effect of the signal at the zero input of the trigger 5p ends (however, the trigger remains in the predisposition) and is blocked by the first input of the AND-NOT k control circuit of the penultimate register, which leads to the termination of the signal at the output of this

an item. Thus, the rewriting signal is removed from the control inputs of the last register, the trigger of the control of the penultimate register is triggered, the output of the corresponding element IS-NOT 4 produces a signal of rewriting to the penultimate register, etc., and the reset circuit retains its state Signal termination: erase input. After the termination of the signal at the write erase input, the trigger of the reset circuit switches to the zero state and the reset circuit returns to the initial state. -

In order to increase the information capacity of the buffer memory, it can be extended by sequential connection of a similar device, for which, inputs 12, 13 and 15 and the outputs of one memory are connected to inputs 1i {, 7 and 8 and inputs ,, of the next memory, respectively.

When a signal is applied to the reset input 10, the trigger of the control circuit of the last code register switches to the initial state, allowing overwriting of information from the previous register. Since the element of the IS-NOT control circuit of the previous register is not blocked, a sequential shift of the information to the last register and the deletion of all information stored in the memory is carried out. .

The m-bit storage registers can be implemented on an RS flip-flop and in the reset circuit there should be an E-flip, ger. All triggers - with inverse control.

Thus, the proposed store-type buffer memory provides an increase in speed due to. ensuring the independence of the sequential transfer of information in the device from the register to the register. after reading from the duration of the write erase signal, determined by the speed of the external device. The speed of information transfer in the storage device is determined by the response time of the logical elements on which it is implemented. In addition, the presence of a reset circuit simplifies the serial connection of the same type of storage device to increase the memory capacity of the RAM, there is the same composition of input and output buses to increase the volume of memory, which must be interconnected in accordance with their functional purpose.

Claims (2)

1. USSR Author's Certificate No. 750565, cl. G 11 C 19/00, 1976. 2. USSR author's certificate number 763970, cl. G 11 C 1S / 00, 1977 (prototype). // L7 f / tt rff 7ff