SU762037A1 - Memory - Google Patents

Description

The invention relates to computing and can be used in the communication paths.

A device containing a shift register, a trigger, delay elements, and AND and OR elements [1] is known. _five

The disadvantage of the device is insufficient reliability, a large delay time of the broadcast signal.

The closest in technical essence to the proposed storage device is a register sequence with ¹⁰ hydrochloric writing and reading, consisting of registers and flip-flops by the number of signal registers, gates · resolution recording, the first input being connected to respective signal outputs zero trig- Gere _15, the second the input of the write enable valves, except for the first valve, is connected to the single outputs of the previous signal / triggers, the second input of the first valve of the write resolution is connected to the “Record” bus, s different inputs of gates 20 are connected to read bus solutions "Reading", second inputs connected to read the valve unit outputs the last register, the outputs of gates permit reading soedi2

yen with the corresponding output tires "Out" [2].

In this device, the shift of information is carried out by the use of additional funds, which adversely affects the reliability of the device, reduces its speed and makes it difficult to perform in the integrated design.

The purpose of the invention is to increase the speed of the device and its simplification.

The goal is achieved by the fact that in a storage device containing storage registers and a control register executed on три-flip-flops, the zero outputs of ΙΚ-flip-flops of the control register are connected to the first inputs of write elements, read elements whose outputs are connected to the device’s outputs, the first inputs of elements reads are connected to the read control bus and to the K input of the last три-trigger of the control register; the outputs of the last ΙΚ-flip-flops of the storage registers are respectively connected to the second inputs of the elements read, write control bus connected to the second input of the first write element, second inputs of the other write elements, respectively 762037

3

four

V-triggers of the control register, and the clock bus, in it the C-inputs of the ΙΚ-flip-flops of the control register are connected to the clock bus, the outputs of the recording elements, respectively, are connected to the 1-inputs of the регистра, -triggers of the control register, I- and K - the inputs of the first ΙΚ, -trigger storage registers are connected to the device inputs, the I and K inputs of each ΙΚ-trigger of the storage registers are connected to the unit and zero outputs of the previous ΙΚ-trigger of the storage registers, the C-inputs of the три-triggers of storage registers respectively podkl cheny to the outputs of the recording element unit ΙΚ-output of the last flip-flop control register coupled to the third inputs of the read elements. The drawing shows a functional diagram of the device.

It contains registers 1, 2 and 3 of storage,

register 4 controls, and storage register 1 consists of 1K-flip-flops 5-6, storage register 2 consists of ΙΚ-triggers 7-8, storage register 3 consists of 1K-flip-flops 9 and 10, control register 4 consists of / of ΙΚ-triggers 11 —13, recording elements 14-16, write control bus 17, read control bus 18, clock bus 19, and read items 20 and 21.

The device works as follows. In the initial state, the triggers 11 —13 of the control register 4 are in the “0” state. The number written to the device is fed in direct and inverse form to the I and K inputs of flip-flops 5 and 6 of the first register 1. At the same time, a recording potential is applied to recording element 14, which, together with the zero output potential of trigger 11 of control register 4, opens recording element 14 and passes to the 1-input trigger 11 register 4 controls. At the end of the first clock pulse, the trigger 1 1 assumes the state "1" and closes the recording element 14, at the output of which the enabling pulse is formed. This impulse arrives at the C-inputs of the triggers 5, 6 of the storage register 1 and records the information of the input buses into this register. The trigger 11, which is in the “0” state, together with the zero output of the second trigger 12 of the control register 4 opens the recording element 15 and sets “1” at the 1 input of the trigger 12 of the control register 4. After the end of the second clock pulse, trigger 12 takes the state "1", and a pulse is generated at the output of recording element 15, allowing overwriting of the information of triggers 5, 6 of storage register 1 to triggers 7, 8 of register 2. This same pulse sets the reset signal to K-input the trigger P of the control register 4, preparing it for receiving the next resolving potential via the write control bus 17. Signal generation of resetting the register triggers is not required, since writing to the registers is performed by a paraphase code.

The operation of the signal trigger 13 of the register 4 control element 16 entries similar to that described above. Each blank register through its entry element and the control register trigger seeks to record information from the higher register, and the filled register protects itself from the new record. In this way, promotion and compaction of information from the input to the output without imposing one number on another is ensured.

The read read signal through the read elements 20 and 21 in the presence of a single signal of the third trigger 13 of control register 4, i.e., when the information is in the third information register 3, reads the number from triggers 9, 10 of the third register 3 and after the end of the next clock pulse resets the trigger 13 of control register 4, which opens entry 16 and passes the write enable signal from the upstream trigger. The rest of the work of the scheme is the same as when writing. If at least in one register there is information, it will advance to the triggers 9, 10 of the third register and will be written off from it by the reading signal.

The use of the proposed device allows to increase the speed, in comparison with the known scheme, by 30%. The exception from the known device of the delay lines allows you to increase the reliability of the RG and to ensure the possibility of performing it in the integrated design.

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Claims (1)

Claim A storage device containing storage registers and a control register executed on три-flip-flops, the zero outputs of ΙΚ-flip-flops of the control register are connected to the first inputs of the write elements, read elements whose outputs are connected to the outputs of the device, the first inputs of the read elements are connected to the read control bus and with the K-input of the last три-flip-flop of the control register, the outputs of the last ΐΚ-flip-flops of the storage registers are respectively connected to the second inputs of the read elements, the control bus a record connected to the second input of the first recording element, the second inputs of the other recording elements are respectively connected to the single outputs of the три-flip-flops of the control register, and a clock bus, characterized in that, in order to improve the performance of the device and simplify it, C-outputs ΙΚ Triggers of the control register are connected to the clock bus, the outputs of the recording elements are respectively connected to the 1 inputs of the triggers of the control register, the 1- and K-inputs of the first-triggers of the storage registers are connected to the inputs of the device, I- and K- inputs of each реги-trigger storage registers five 762037 connected with unit and zero outputs preceding ΙΚ-flop registers snoring, C inputs of flip-flops ΙΚ-snoring registers respectively connected to the outputs of the recording element unit ΙΚ-output of the last flip-flop control register ₅ soedi- nen with third inputs of the read elements.