SU493805A1 - Buffer storage device - Google Patents

Description

There are 5 conclusions. The clock inputs of registers 1 are connected to the bus 6 pulses of the first cycle.

The output of the element "PI 7 write resolution is connected to the inputs of the input device 2, and the output of the element" AND 8 read resolution is connected to the inputs of the output device 3. In this case, the inputs of the elements “And 7 and 8 are connected to the output of the additional element“ And 9, the inputs of the element “And 9 - with the corresponding outputs of the bits of the counter 10 of the register address, to which the bus 11 is also connected. installation. The input of the counter is connected with the output of the element "OR 12", the input of the element "OR - with the bus 6 pulses of the first cycle and the output of the imager 13 single pulses. The inputs of the imaging unit are connected to the write buses 14, reads 15 and the bus 16 of the pulses of the second cycle. Tires 14, 15 and the output of the imaging unit 13 are also connected to the inputs of the synchronization unit 17, the write output 18 to the input of the element "And 7, the output 19 of the readout - to the input of the element" And 8.

Each register 1 consists of bits 20-23, and the counter 10 - of bits 24 and 25.

When the memory is running in the buffer mode, the processes of writing and reading information are usually alternated. For simplicity, let us consider the processes that occur, when recording information 1010, only in one shift register (bit). The work of the other registers is similar.

When the counter 10 is in its initial position, the signal "O on bus 11, the outputs of bits 24, 25 of the counter are set to" O. With the arrival of a clock pulse on bus 6, both bits 24 and 25 go to state "1", detected by the element "AND 9, at the output of which a signal appears. If the counter operates only from the pulses of the first clock cycle on bus 6, then element “AND 9” is triggered every four pulses, marking the zero phase state of the counter. With the arrival of information “1 via bus 4, it is fed to the input of input device 2. At the same time, a write signal arrives on the write bus 14, it acts on the shaper of 13 single pulses, which produces one pulse synchronized with the pulses of the second cycle on the bus 16.

This pulse, passed the element "OR 12", is fed to the input of the counter 10, changing its phase state, with respect to "zero. Now both bits 24, 25 go to the “single state after three pulses of the first cycle (the fourth pulse is the driver pulse). At the transition of bits 24, 25 to the state “b”, the element “And 9” is triggered and the signal from its output goes to the inputs of the elements “And 7 and 8. Signals from the synchronization unit 17 are supplied to the other inputs of these circuits. The recording signal received at the input of block 17 via bus 14 is synchronized by the shaper signal so that at the output 18 of this block a write signal appears only at the end of the pulse from the shaper. When the signals at the input of the element "And 7 of the recording resolution coincide, it is triggered and a signal is sent to the input of the input device 2 allowing the recording of information" 1 for the first time (20) of register 1.

After filling the register, since the capacity of this accumulator is equal to the number of states of the address counter, the counter is again in the "zero phase state and

10, you can begin the process of reading information.

With the arrival of each read signal on the bus 15, the driver and the pulse from its output changes step by step

15 phase meter status. Element "9" and a synchronization block are triggered with each read signal, and the read signal synchronized by the shaper signal (on the falling edge) appears on

20 output 19 of the block 17.

When the signals on the element "AND 8" coincide, an output readout signal is formed at its output, under the influence of which the output device 3 is opened. The information that at that moment was in the last bit (23) of the register appears on the output bus 5. During the reading, the information comes out of the accumulator in the same order in which it was recorded (buffer memory mode). The duration of the output signals is equal to either the repetition period of the pulses of the first cycle or the time between the trailing edge of the pulse of the second cycle and the trailing edge of the standing pulse

5 first bar. As in all cyclic memories, in the proposed BZU there is a minimum time of writing and reading information in the shift register. Duration of the input signals of recording and reading and information signals

0 must be equal to Г + Дтсинхр., Where Т is the period of information circulation in the register; Atsinkhr. - delay of the write and read signals in the synchronization unit. The synchronization block is easy to perform, for example, two / - / (- triggers. The inputs / and R of one of them are given recording signals, the inputs / and / of the other are read signals, the clock inputs of both triggers are output from the driver, and pa inputs

0 K - levels “O. With this construction of the synchronization circuit, single write and read signals at the outputs Q of the flip-flops appear at the end of the pulse from the driver and end with the end of the write signals

5 and read. The former is a conventional scheme on two / - / (- (or other type) triggers.

The presence in the BZU of a single pulse generator, the elements of "AND 9 and" OR 12, which allowed to realize the phase indication for writing and reading information into the shift register, makes it possible to reduce the amount of necessary equipment to control the register drive and make it independent