JPH0411388Y2 - - Google Patents

Description

[Detailed description of the invention] "Industrial application field" This invention is used, for example, in a testing device for semiconductor integrated circuits, and generates a rate signal with a set period, and also generates a rate signal with a set period between each adjacent rate period. This invention relates to a timing generator that generates periodic multi-locks.

``Prior Art'' A timing generator in a conventional semiconductor testing device generates one clock, or rate signal, in one test cycle, or so-called rate cycle. However, depending on the target semiconductor device, a plurality of clocks may be required during the rate period, and such clocks are called multi-clocks.

A conventional timing generator for generating multiple clocks was constructed as shown in FIG. For example, cycle designation data and clock number designation data are stored in advance from the control unit 11 through the bus 12 in a clock cycle data memory 13 as a clock cycle setting means and a clock number data memory 14 as a rate cycle setting means, respectively. .
In response to the time slot designation signal applied to the bus 12, one each of cycle designation data and clock number designation data is read out from the cycle data memory 13 and the clock number data memory 14, respectively. The read cycle designation data is sent to the multi-clock generation circuit 15.
is input. The multi-clock generating circuit 15 receives the reference clock through the terminal 16 of the control section 11, generates a multi-clock having a period corresponding to the period designation data, and outputs it to the multi-clock terminal 17.

The multi-clock at this terminal 17 is branched into a rate signal generation circuit 18, and the rate signal generation circuit 18 is provided with a counter 19.
is the multi-clock, clock number data memory 1
When the number corresponding to the clock number designation data from 4 is counted, a rate signal is output to the rate signal terminal 21. For example, the counter 19 is a down counter that can be preset, and when the zero detection circuit 22 detects that the counting state of the counter 19 has become zero, its output becomes a high level, which causes the gate 23
given to. The multi-clock outputted in this state passes through the gate 23 as a rate signal and is outputted to the rate signal terminal 21. The counter 19 counts the next multi-clock and the zero detection circuit 22
When the output becomes low level, the clock number designation data is preset in the counter 19 at the falling edge. This preset clock number designation data is sequentially decremented by 1 each time a multi-clock occurs. Therefore, a rate signal is obtained at the terminal 21 every time a multi-clock number corresponding to this clock number designation data is generated.

For example, as shown in FIG. 7A, the rate signal terminal 2
1, a rate signal is obtained for each time slot, and multi-clocks are generated at equal intervals between adjacent rate signals, as shown in FIG. 7B. The period of this rate signal and the period of the multi-clock are changed by changing the time slot designation signal from the control section 11. The control section 11 can only change the time slot designation signal for each time slot. Therefore, for example, as shown in FIG. 7, the period of the multi-clock can be set to _R0 in the 0th time slot, and the period of the multi-clock can be changed to _R1 in the next 1st time slot.

``Problem to be solved by the invention'' Recently, however, it has been required to change the period of the multi-clock during one rate period, that is, during one time slot.

The purpose of this invention is to provide a timing generator that can change the period of a multi-clock within one rate period.

"Means for Solving the Problem" According to the present invention, a clock cycle auxiliary signal generation circuit is provided, the clock cycle auxiliary signal generation circuit is provided with an auxiliary memory, and the auxiliary memory is read out by a counter that counts multiple clocks. . The data read from the auxiliary memory is applied as an output of the clock period auxiliary signal generating circuit, that is, an auxiliary signal, to the clock period setting means, and the clock period setting means changes the clock period designation data in accordance with the auxiliary signal. Therefore, depending on the contents stored in the auxiliary memory in the clock period auxiliary signal generating circuit, it is possible to change the period of the multi-clock generated for each multi-clock, for example.

Embodiment FIG. 1 shows an embodiment of a timing generator according to this invention, and parts corresponding to those in FIG. 6 are given the same reference numerals. In this example, the down counter 2, which can be preset, is used as the multi-clock generating circuit 15.
5 is provided, and when the count value of the down counter 25 becomes zero, it is detected by the zero detection circuit 26, and its output is sent to the multiclock terminal 1 as a multiclock.
7 and is applied to the load terminal of the counter 25 through the OR gate 27. In addition, the readout output of the periodic data memory 13 and the register 3
0 data is selected by the multiplexer 28 and supplied to the down counter 25 as preset data. An initialization signal is generated from the control section 11 through the terminal 29, and this initialization signal is applied to the load terminal of the counter 25 through the OR gate 27 to preset it, and the rate signal generation circuit 1
8 to the clear terminal of the counter 19 to set it to zero. Further, in order to control the count of the counter 19 as necessary, the reference clock of the terminal 16 can be supplied to the clock terminal, and a clock can also be supplied from the control section 11 to the clock terminal through the OR gate 31.

In this invention, a clock period auxiliary signal generating circuit 32 is provided. This clock cycle auxiliary signal generation circuit 32 is equipped with an auxiliary memory 33,
The auxiliary memory 33 is read out according to the counting state of the multi-clock during one time slot. In this example, a dedicated up counter 34 is provided for reading out the auxiliary memory 33.
4 is cleared by the rate signal at the rate signal terminal 21 and counts the multi-clock signal at the terminal 17. The count value of the counter 34 is read out from the auxiliary memory 33. The output of this auxiliary memory 33 is given to the clock cycle setting means 13 as the output of the clock cycle auxiliary signal generating circuit 32. The contents of this auxiliary memory 33 can be rewritten as necessary.

The operation shown in FIG. 1 will be explained in detail. For example, the periodic data memory 13 has an address input of 8 bits,
The output data is 5 bits, and n-1 is set for the clock cycle nT (T is the cycle of the reference clock at the terminal 16) to be generated. The clock number data memory 14 has 4 bits of address input and 5 bits of output data, and is set to a value subtracted by 1 from the number of multi-clocks to be generated within the rate period. The auxiliary memory 33 has 4 bits of address input and 4 bits of output data, and its output data is outputted as an auxiliary signal forming part of the input address of the clock cycle data memory 13. counter 19,2
Both 5 and 34 are 5-bit counters. For example, as _{shown in FIG .}
is set, and the clock number data memory 14 stores output data D ₀ to D ₄ for the addresses A ₀ to A ₃ as shown in FIG. Address A ₀ to
Assume that data D ₀ to D ₃ are stored for A ₈ .

When an initialization pulse is outputted to the terminal 29 as shown in FIG. 3A, in this example, 1 of the register 30 is selected by the multiplexer 28, the counter 25 is preset as shown in FIG. 3C, and the zero detection circuit is 26 (terminal 17) is at a low level "0" as shown in FIG. 3D, and the counter 19 is cleared to zero as shown in FIG. 3E.
The output of the zero detection circuit 22 is at a high level "1" as shown in FIG. 3F.

In this state, when a reference clock is input from the terminal 16 as shown in FIG. 3B, the counter 25 is subtracted by 1 by the first reference clock, and its output becomes zero as shown in FIG. 3C. The output of the zero detection circuit 26 becomes a high level, and as shown in Fig. 3 D and G.
As shown in the figure, the multi-clock of terminal 17,
Each rate signal of 1 rises (becomes high level "1"). The counter 34 is cleared by the rising edge of the rate signal, and the output of the counter 34 becomes zero as shown in FIG. Thus, the output of the auxiliary memory 33 becomes zero as shown in FIG. 3I. This auxiliary signal and the time slot designation signal (K in FIG. 3) of the bus 12 are applied to the periodic data memory 13 as addresses A ₀ to A ₃ and A ₄ to A ₇ . The output of 13 becomes 1 as shown in FIG. 3J.

Next, when the second reference clock is input, the count value of the counter 25 is no longer zero, so the output of the zero detection circuit 26 becomes a low level as shown in FIG. 25 is the period designation data from the memory 13. In this example, 1 is preset as shown in FIG. 3 J, and the result is as shown in FIG. Then, the output of the zero detection circuit 22 goes to a low level as shown in FIG. The output of the counter 19 becomes 5 as shown in FIG. 3E. The rate signal also falls as shown in FIG. 3G.

Next, when the third reference clock is input, the contents of the counter 25 become zero as shown in FIG. 3C, the multi-clock rises again as shown in FIG. 3D, and the counter 34 advances by one step. Figure 3H
1 as shown in , and in this example, the auxiliary memory 3
The output of 3 is also 1 as shown in FIG. 3I. However, since the contents of the periodic data memory 13 are as shown in FIG. 2A, its output remains as 1 as shown in FIG. 3J. In this way, the multi-clock at terminal 17 alternates between high and low levels each time the reference clock is input. When the fifth reference clock is input and the counter 34 counts 2 as shown in FIG. 3H, the auxiliary signal becomes 2 as shown in FIG. 3I. Therefore, the readout output of the periodic data memory 13 changes from 1 to 3 as shown in FIG. 3J. Therefore, at the next 6th reference clock, the counter 25 receives the signal shown in FIG.
3 is preset as shown in FIG. Therefore, when three reference clocks are input after the sixth reference clock is input, the value of the counter 25 becomes zero, that is, when the counter 25 counts the ninth clock in the serial number of FIG. 3B, counter 25
The count value becomes zero as shown in FIG. 3C, and a multi-clock occurs as shown in FIG. 3D.
In other words, the period of the multi-clock was 2T until then, but now it is 4T.

Similarly, each time a multi-clock occurs, the count value of the counter 34 changes as shown in FIG. 3H, and the auxiliary memory 33 is read out using the changed count value as an address. Therefore, auxiliary memory 3
3 or by selecting the storage contents of the period data memory 13, the period of the multi-clock can be freely changed for each clock.

The multi-clock is counted by a counter 19, and the counted value is sequentially subtracted for each multi-clock as shown in FIG. 3E. In this example, when six multi-clocks occur, the count value of the counter 19 becomes zero, and the output of the zero detection circuit 22 becomes the third
The level becomes high as shown in Figure F. Therefore, when the next multi-clock occurs, the rate signal is output to the terminal 21, and at the falling edge of the signal, the clock number instruction data (FIG. 3L) in the clock number data memory 14 is preset to the counter 19. Control part 1
The rate signal of the terminal 21 is inputted to the terminal 1, and the time slot designation signal outputted to the bus 12 can be changed for each rate signal. In this example, three multi-clocks with a period of 2T are generated for one time slot period, that is, between one adjacent rate signal, two multi-clocks with a period of 4T are generated, and then two multi-clocks with a period of 2T are generated. .

The period of these multi-clocks and the number of each clock can be changed arbitrarily by selecting the data stored in the memories 13, 14, and 33. Generally, for example, the multi-clock is set at a certain time slot for the rate signal shown in FIG. 4A. As shown in Figure 4B _{, the} period is changed _{to R 00} , R ₀₁ , . The period of the signal) can also be changed, and the number of multi-clocks occurring within a time slot can also be freely chosen.

The clock period auxiliary signal generation circuit 32 can read out the auxiliary memory 33 according to the counting state of the number of multi-clocks that are sequentially generated within one rate signal period (time slot period). As shown in FIG. 5, it is also possible to read out the auxiliary memory 33 according to the counting state of the counter 19 in the rate signal generating circuit 18. However, in this case, in order to generate the same multi-clock as shown in FIG. 3, it is obvious that the relationship between the data in the auxiliary memory 33 and the addresses must be the same as in FIG. 2C. Furthermore, in the above example, a plurality of clock period data are stored in the period data memory 13 serving as a clock period setting means, and this memory 13 is used to combine the time slot designation signal of the bus 12 and the auxiliary signal from the auxiliary memory 33. Although the clock cycle is read by address, for example, a register that can be set via a bus or manually is provided as a clock cycle setting means, and the data in the register and the auxiliary signal read from the auxiliary memory 33 are combined to be used as clock cycle data. good. Alternatively, the clock period may be determined only by the auxiliary signal read from the auxiliary memory 33.

The counters 25 and 19 used in the multi-clock generation circuit 15 and the rate signal generation circuit 18 do not necessarily have to be down counters, but each data from the clock cycle setting means and the rate cycle setting means can be preset in a presettable up counter. A carry output may be detected, and in that case, the data to be set accordingly may be preset to the counter as the complement of the maximum count value of the counter, or the count value of the up counter and the count value of the up counter may be preset. A match may be detected by comparing input clock cycle designation data or clock number designation data.

``Effects of the Invention'' As described above, the timing generator of this invention can generate a plurality of multi-clocks for each rate signal, and can change the period of the multi-clock within one rate period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a timing generator according to this invention, and FIG. 2 shows its memory 13,
14 and 33, FIG. 3 is a time chart showing an example of the operation of FIG. 1, and FIG. FIG. 5 is a block diagram showing another embodiment of the invention; FIG. 6 is a block diagram showing a conventional timing generator; FIG. FIG. 3 is a diagram showing an example of a rate signal and a multi-clock. 11... Control unit, 12... Bus, 13... Clock cycle setting means, 14... Rate cycle setting means, 15... Multi-clock generation circuit, 16...
Reference clock input terminal, 17...Multi clock output terminal, 18...Rate signal generation circuit, 19,
25, 34... Counter, 21... Rate signal output terminal, 22, 27... Zero detection circuit, 32...
Clock cycle auxiliary signal generation circuit, 33... auxiliary memory.

Claims (1)

[Claims for Utility Model Registration] A multi-clock generating circuit generates a multi-clock with a period corresponding to the setting data of the clock period setting means, and the multi-clock is converted into clock period specifying data from the gate period setting means in a rate signal generating circuit. In a timing generator that generates a rate signal every time a corresponding number of clocks are counted, the data is read out in accordance with the count value of the counter that counts the multi-clock, and changes the clock cycle designation data from the clock cycle generation means. 1. A timing generator comprising a clock cycle auxiliary signal generation circuit that outputs auxiliary data.