SU1413676A1 - Self-check direct-access memory - Google Patents

Description

The invention relates to computing and should be used in the construction of storage devices with self-control.

The purpose of the invention is to increase the speed of the device during self-control.

The drawing shows a block diagram of the proposed device.

The operative self-monitoring memory contains block 1 of RAM, outputs 2. device data, comparison block 3, adder 4 modulo two decoder 5, counter 6, second trigger 7, input 8 Device sampling resolution, input 9 Read / write, address inputs 10 inputs 11 dataJ generator 12, input 13 Control / operation of devices a ,, first ™ trigger 14, block 15 reset, display element 16, one-shot 17, multiplexer 18, element OR NOT 19 ,.

Block 1 of the RAM is built on the LSI OZU- and has the organization N X M, where N is the number of addresses, and M is the data word width

It is known that the MARSH test algorithm for RAM with the organization N x 1 is closed in two passes of the address space. In this case, during the first pass through each ap, res, the operations Ij Record O, Record 1 are executed, and in the second pass Read O, Record 1 Since the output response of the RAM is determined by the true table, the input data signals during both the first and second addresses of the addresses are kept unchanged (o and 1, respectively) for the required liver operations. Record O and Record 1% based on signals Sampling resolution (PB) , TH / ZP and Dgx, at any time, you can specify the output code of the correct RAM, for example, when TH / ZP O and the operation is performed. Permission () read NIN (TH / ZP 0) zero (Dg,. (L ) and, consequently; the output signal of an operative RAM must be O (direct output) "With a multi-bit data word (Mx-1) and stimulation of the RAM data inputs, the outputs of the decoder are controlled by the bits of the counter following the ones. digits stimulating memory addresses (diagonal data search) one pass

that consists of 2. M of address passes. Here, during the control of each bit, redundancy takes place, consisting in additional operands Read 1, Write 1 (with the active signal level at the decoder output - logical) in all not the first passes of addresses after changing the input data into the bit de.

At the same time, the information read from the operative memory unit 1 is identical to the information found at its inputs in the previous address pass, and can be obtained by cyclically shifting the information available at the inputs 20

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passage of addresses. For example, when the state of the Dpcoo Dm inputs of the RAM is 1 0. 1 ,,, 1, a reference clock is formed by a cyclic shift - 1 o .. 1 0, which corresponds to Read O for the senior bit and Read 1 for the remaining bits The outputs of the decimator 5 are connected to a cyclic LM by shifting the lower outputs to the inputs of the comparison unit 3 The lower output of the decoder 5 is connected to the senior input of the second group of inputs of the comparison unit 3, and all other outputs of the decoder are connected to the lower outputs of the lower outputs to the remaining inputs 3 of the comparison .

The single-oscillator 17 brakes the generator 12 for the time required for you to select the RAM unit 1. This is done because the oscillator frequency 3 2 is chosen such that the duration of the clock cycle of the generator 12 is determined only by the full switching time} of the bits of the counter 6. At the same time, the time between the nearest signals is reduced to a minimum. The result in the second Tpvirrep 7 of the result of comparing the output and the second response of block 1 of the RAM, which is formed by the block 3 of the comparison; is performed only with the active signal level. The sampling resolution in the Read mode, t, e, is monitored only by the read information.

The generator 12 generates clock pulses for counter 6 during self-monitoring. The first trigger 14 serves for

blocking the operation of second trigger 7 during the first pass of addresses. This is due to the fact that when power is supplied, the random access memory is oriented arbitrarily and may have incorrect information at the output. After the first pass of the addresses, all the memory cells are set to an unambiguous state.

The device works as follows.

When power is supplied, the pulse from reset unit 15 sets the counter 6 to d and the trigger 14 to. The last causes reset of trigger 7 and the formation of the display OK. The device’s further operation is determined by the signal at input 13 Control / operation. In the Operation mode, logic 1 at input 13 blocks the generator 12, determines the operation of counter 6 in the asynchronous installation mode for data inputs, and the operation of multiplexer 18 in the information transfer mode from the second group of inputs Bo., OBj. Thus, the PB, CT, and PD signals and addresses through the counter 6, and the data through the multiplexer 18 are fed to the corresponding inputs of the RAM unit 1, which ensures its operation in the normal mode (since the modules RB and 2 receive the inputs of modulator 2) logical, then its output repeats the signal PB). Since generator 12 is blocked, the state of the second trigger 7 and the display element 16 remains unchanged. In the Control mode, a logical O at input 13 enables the operation of generator 12, determines the operation of counter 6 in continuous conversion mode (generator 12 operates in self-oscillatory mode) and the operation of multiplexer 18 in transmission mode from inputs. In this case, the state of the counter 6 does not depend on the signals on its data inputs, and the state of the outputs of the multiplexer 18 does not depend on the state of the signals on its inputs B - .., B. Since the stimulus is targeted

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the inputs of the RAM block 1 are performed by the bits of the counter 6 starting from the 3rd one, then the duration of the call to the RAM block 1 is 8 clock cycles of the generator 12 (the state of the counter 6 varies on the leading edge of the clock signal). During the first four cycles, Read operation was recorded, for the second - Record

Inside each four-stroke operation, a push-pull PB signal is inserted (produced by sumatter 4 modulo two), which produces an active level at the same remaining signals,

served on the RAM block (thereby achieving the correct timing diagram).

When the active level of the signal RV appears, the one-vibrator 17 generates a pulse during which the generator 12, and hence the counter 6, is blocked, an increase in the duration of a given generator clock, which is allotted to perform the operation, occurs. Reading or Writing for a single-pulse time which is chosen not less than the memory sampling time. The increase in the remaining three clock cycles of the generator 12 during the development of four-stroke operations Record or Read does not occur.

Stimulation of data inputs of block 1

operating memory is carried out through a multiplexer 18 by a depotfrautor 5 f controlled by the second group of outputs of counter 6, which corresponds to testing of block 1 of operative py-mi according to the MARS algorithm with diagonal enumeration of data. Since each pass of the address is readable from block 1 of operative memory Since the information corresponds to the state of the outputs of the decoder 5 in the previous passage of addresses, the reference is formed by applying cyclically shifted towards the lower outputs of the decoder 5 to block 3 of the comparison. So

as when the power supply of the cell of the memory 1 is set to an arbitrary state, during the first pass of the addresses, the output response of the memory 1 is not monitored (the first trigger 14 keeps the single state keeping the second trigger 7 in the reset state) The completion of the first pass of the addresses causes the return of the bits of the counter 6 to the state O, the back front at the exit of its (n + 2) -th bit translates the first trigger -14 to the state O, allowing the operation of the second trigger

pa 7 on the sync input. The synchronization input of the second flip-flop 7, without an OR-NOT 19 element, controlled by the Read / Write signal, receives pulses from the inverse code of the one-oscillator 17. During the Read operation, the passage of the single-oscillator 17 through the element 19 to the synchronization input of the Second the trigger 7, and during the Write operation, is blocked, which ensures that the second trigger 7 of the Signal from the output of the comparison block 3 is recorded only when information is read from the random access memory block. The Comparison Signal is O when the data in the first group of inputs of the Comparison Unit 3 (information read from the RAM memory block B) coincides with the data of the second group of its inputs, the reference reaction) and is equal to 1 if they do not match.

: When the operative memory unit 1 is intact, the B-input of the second trigger 7 receives zeros, and its state, and, consequently, the state of the display element 16 does not change. If at least one discrepancy is detected, the trigger 7 is set to the logical state. An indication is generated, the faulty K is blocked by the generator 12, i.e. the test stops at the address of block 1 of the RAM, where a fault has been detected

Claims (1)

Invention Formula A self-monitoring random access memory containing a memory block whose outputs are connected to the inputs of the first group of the comparison block and are information outputs of the device, a generator whose first input is connected to the Control / operation input of the device, and the output is connected to the counter synchronization input, and the zero and second bits of the information input of the counter are the inputs Allow sampling and Read / write the device, respectively, the first digit of the information input of the counter is connected to the zero potential bus, bits from the third to (n + 2) information inputs of the counter are the device's address inputs, the meter installation input is connected to the first generator input and the installation input to the unit state of the first trigger and, is the device reset input, 0, the first and second outputs of the zero and first bits of the counter are connected to the inputs of a modulo two adder, the output of which is connected to the sample input of a real-time block crystal 5 memories, bits from the third to (n + 2) counters are connected to the address inputs of the RAM, the output of the comparison block is connected to the information input of the second trigger, the output of which is connected to the second input of the generator and is the indicator output of the device, and the input of the installation of the second trigger is connected to the output of the first trigger, 5 characterized by the fact that, in order to improve speed at self-control, a descrambler, a single-oscillator, an OR-NOT element, a multiplexer are entered into it, and the decoder's inputs are connected to the outputs of bits from (n + 3) to (n + 2 + k) the counter, the outputs of the decoder are connected to the information inputs of the first multiplexer group and to the corresponding inputs of the second group of the comparison unit, the information inputs of the second group of the multiplexer are device data inputs, the multiplexer outputs are connected to the data inputs of the block Q RAM, the control input of the multiplexer is connected to the Control input / device operation, the one-shot input is connected to the output of a modulo-two adder, direct output with one-shot connected to the third generator input, inverse output. the one-shot is connected to the first input of an OR-NOT element, the second input of which is connected to the output of the third digit of the counter, the output of the IPI element is NOT connected to the sync input of the second trigger, the sync input of the first trigger is connected to the output of the (n + 2) counter discharge. five 0