SU1053165A1 - Device for checking working memory - Google Patents

Abstract

A DEVICE FOR CONTROL OF OPERATIONAL MEMORY, containing a clock pulse generator, the output of which is connected to the synchronous input of the signal analyzer, whose information input is the output of the device, characterized in that, in order to increase its speed, reliability of control and simplification, enter it. : we are a decoder, an adder unit modulo two, a multiplexer, an OR element, an adder modulo two and a counter, the input of which is connected to the output of the clock generator, and the outputs are connected to the inputs of the decoder, adder unit modulo two, the multiplexer, to the first input of the adder by module two, to the first input of the OR element, the second input of which is connected to the multiplexer output, the modulo adders block inputs are two connected to the multiplexer inputs, the second modulo adder two input connected to the higher-order output counter and to the input of signal analyzer Startstop outputs (A decryptor, the block adders modulo two., OR element, modulo two adder and an output MSB of the counter devices are the outputs.

Description

ate

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The invention relates to memory devices and can be used for functional control of both individual microcircuit packages, random access memory (RAM), and arrays of semiconductor RAM of arbitrary capacity and organization built on their basis.

Devices are known based on the use of a computer or computer-based controllers for storing the program of input effects of test procedures of RAM chips, as well as for implementing the process of controlling output reaction of test chips of RAM ij.

The disadvantages of these devices are cumbersome and difficult to carry out functional control by any method. Besides . Moreover, the disadvantage of these devices is incomplete testing, since the control of the microcircuits is performed only on the basis of readable information, the remaining states of the truth table are not taken into account,

The closest technical solution to the invention is a device for monitoring a semiconductor memory, comprising a clock, a pulse generator, a timing diagram, a comparator, a signal analyzer, a drive and a control unit h.

The disadvantages of the known device. there are large hardware costs and low speed of operation due to the fact that considerable time is required to detect faults. In addition, the device has a low reliability of control, since the control does not take into account all the states of the truth table of the tested chip, and only the read resolution mode is checked, in addition to which there are the forbidding, disallowing, recording permission modes, the output states at which it is also necessary to monitor when testing.

The aim of the invention is to increase the speed and simplify the device, as well as increase the control quality.

This goal is achieved by the fact that a memory monitoring device containing a clock generator, the output of which is connected to the synchronous input of the signal analyzer, whose information input is the output of the device, is entered a decoder, modulo-two block, multiplexer, element or modulo-adder two and a counter, the input of which is connected to the output of the clock generator, and the outputs are connected to the inputs of the decoder, the block of adders modulo two, the multiplexer, to the first input of the modulo adder two, - to the first input of the element. OR, the second input of which is connected to the multiplexer output, the inputs of the modulo adders block are two connected to the multiplexer inputs, the second input of the modulo adder two is connected to the high-end output of the counter and the signal-analyzer outputs, the decoder outputs , modulo two adders, the OR element, modulo two adders, and the high-order output of the counter are outputs of the -device.

The drawing shows a functional diagram of the device for controlling the RAM by a logarithmic test.

The device contains a generator of 1 clock pulses., The output of which coe is zenin with the input of (binary) counter 2 with the number of bits 1 + 5 + x (where is the number of address inputs of the controlled random access memory; X is the number of control inputs of the multiplexer) its outputs are connected to the decoder 3, to the unit 4 modulo two adders, to the multiplexer 5, the output of which is connected to the first input of the element OR 6. Counter 2 is also connected to the second input of the element OR bis by the first and second inputs of the adder 7. module two. The outputs of the decoder unit 4 modulo two adders, the element OR b and the adder 7 modulo two, are connected to a controlled random access memory 8 and are outputs of the device. The inputs of the adder unit 4 modulo two are connected to the multiplexer 5 inputs. The output of the operational memory 8 is connected to the information input of the signal analyzer 9, the synchronous input of which is connected to the generator 1 output, and its start-stop input is connected to the highest bit of the counter. and to the second input of the adder 7 modulo two.

The signal analyzer is a 3W signature analyzer.

Structurally, the device is designed so that the on-line memory 8 is connected to the elements of the device and the signal analyzer 9 by means of an interface switching matrix 10 different for different base case (shown by dashed line).

The device works in the following way ..

Generator 1 starts a counter which, in continuous recalculation mode, with the help of you 1 bit decoder

and

torus 3, generates successive signals of the decrypted statuses O, T,,: each of a clock cycle (period) duration and having zero active values. One of these signals is status 2 is. It is used as a sample resolution signal of monitored random access memory. This generation of a sample resolution signal ensures that its switching takes place within the Read / Write signal, and, most importantly, after the addresses have been switched. The outputs of bits 2, ..., (1 + 1 of counter 2 are the bits of the address group, which, depending on the control bit AND + 4, loop through the addresses in the forward or reverse direction.

The bit (1 + 2 counters is designed to lock the record, i.e., so that a read occurs at each second address search cycle. The bit 1 + 3 counter 2 generates data, the phase of which varies depending on from the jll + 5 + X bit, i.e., if in the first half of the test the data changes from zero to one unit, then to the second - from one to zero, bits h + 5, ..., and + 4 + X counter 2 is fed to the control, and the multiplexer inputs are intended

to change the Gp for each sequential enumeration of addresses) the duration of the write and read by alternately switching to the input Write the reading of the bits of the address group

counter 2.

As a result, the RAM matrix is monitored in accordance with a logarithmic test. In addition, by introducing the element OR 6

0, after each address enumeration, a check reading of the RAM matrix is performed, which expands the testing ability of the test.

The output of the controlled random access memory 8 is fed to the information input of the signature analyzer 9 used as a signal analyzer, the Start Stop input of which is controlled from the old bit of counter 2, and the synchronous input receives synchronization signals from the clock pulse generator 1. Using the signature analyzer 9 provides the ability to control the OUTPUT reactions of the RAM, not only during the reading, but, what is especially significant, under all possible conditions of the truth table of the controlled RAM, 8

0 namely, when recording is disabled, when writing is enabled, when reading is disabled and when reading is allowed. The existing redundancy of particular importance does not have to do with the use of signature analysis, all of which provide compression of binary information of arbitrary length with very high confidence.

Claims (1)

DEVICE FOR MONITORING OF RAM, containing a clock pulse generator, the output of which is connected to the synchro input of the signal analyzer, the information input of which is the output of the device, characterized in that, in order to increase its speed, reliability of control and simplification, it is entered into. They are a decoder, an adder block modulo two, a multiplexer, an OR element, an adder modulo two and a counter whose input is connected to the output of the clock generator, and the outputs are connected to the inputs of the decoder, adder block modulo two, multiplexer, to the first adder input modulo two, to the first input of the OR element, the second input of which is connected to the output of the multiplexer, the inputs of the adder block modulo two are connected to the inputs of the multiplexer; the second input of the adder modulo two is connected to the output of the high-order bit of the counter and to the Start- $ stop input of the signal analyzer, the outputs of the decoder, the adder block modulo two