RU1800458C - Test forming device - Google Patents

Abstract

The invention relates to computer technology and can be used in the construction of monitoring systems and diagnostics of complex digital devices. The aim of the invention is to expand the functionality by maintaining fixed levels of logical signals at randomly selected device outputs in a pseudo-random testing cycle. 4 ill., 1 tab.

Description

The invention relates to computer technology and can be used in the construction of monitoring systems and diagnostics of complex digital devices

The purpose of the invention is to expand the functionality by storing fixed levels of logic signals at randomly selected device outputs in a pseudo-random testing cycle.

In FIG. 1 is a functional diagram of a test generating apparatus; Fig. 2 is a functional diagram of a control unit; in FIG. 3 is a timing diagram of signals generated by a control unit in a mode for setting initial conditions; in FIG. 4 - the same, in operating mode.

The device for generating tests comprises a control unit 1, a parity element 2, and a shift register 3 forming a pseudo-random sequence generator with zero initial conditions, a one-bit memory unit 4, a bus former 5, a first decoder 6, a multi-charge memory unit 7, a second decoder 8, group 9 of adders modulo two, register 10 with three output states, group 11 of output registers, inputs of device data 12, address inputs of device 13, input 14 of device startup, inputs 15 of the cycle duration vani pseudo-random test, outputs 17 of the device.

The control unit 1 contains a counter 1.1 test words, a clock 1.2, a trigger 1.3, a switch 1.4, a first element AND 1.5, an address counter 1.6, a delay element 1.7, a constant memory element 1.8, a register 1.9 and a second element 1.10 I.

The element 1.8 of read-only memory can be implemented, for example, on two chips of the ROM ROM 155 REZ, programmable in accordance with the table in which the symbols indicate:

+ - indifferent state:

O is a logical zero;

1 logical unit

The device operates as follows.

Work is possible in two modes. In the initial conditions setting mode, information is recorded in the output registers of group 11 and their corresponding

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unit 7 memory cells. Binary information corresponding to the allocation of addresses to the bit outputs of the device is entered into the single-bit memory cells of unit 4. In this case, the level of the logical unit recorded in the memory cell of unit 4 corresponds to an unchanged signal level at the corresponding output of the device in the pseudo-random test synthesis cycle. The logic zero level recorded in the memory cell of unit 4 corresponds to the output of the device with a variable signal level in the pseudo-random testing cycle. To implement the mode at input 16, the MODE is set to zero signal level. At the inputs 13, an address is established that defines the output register of group 11, the corresponding memory cell in block 7, and the memory cell in block 4, corresponding to one of the bits of the addressed register. At the inputs 12, the data entered in the addressed output register, the unit block 7 and the unit 4 cell is set. In this case, the information entered in the unit 4 is set on the first of the inputs 12. The above data settings and addresses are accompanied by a short single pulse at the input 14 of the START devices. The trigger is set to a single state by trigger 1.3 in the control unit 1, which allows the passage of pulses from the clock 1.2 through the J / I 1.5 element to the summing input of the address counter 1.6. The latter changes its state in the direction of magnification. The presence of register 1.9 in the control unit 1 is necessary to eliminate the states at the outputs of the read-only memory element 1.8 when the addresses are modified. The delay element 1.7 compensates for the intrinsic time delays of elements 1.6 and 1.8, ensuring the synchronization of register 1.9 at the time of steady-state signal levels at the outputs of the constant memory element 1.8.

Timing diagrams of the control unit 1, which corresponds to the contents of the first memory bank of the element 1.8 in the initial setting mode, are shown in FIG. The signal register 3 is transferred to the recording mode of parallel information. After the first pulse F, the signal C1 is set to a single state, on the leading edge of which the previously set address is recorded in register 3. At the same time, the bus driver 5 is selected by the CSBD, WRRAM1, WRRAM2 signals and the memory blocks 4 and 7 are prepared for recording. Data through the bus driver 5 is transmitted to the inputs

of group 11 registers and inputs / outputs of block 7. After the second pulse F, at a zero level of signals CSRAM1 and CSRAM2, the data are written into memory blocks 4 and 7. At the same time, along the rising edge of the C3 signal to one of the output registers of group 11 in accordance with a single signal at one of the outputs of the decoder 6 records data that are the initial conditions for a pseudo-random test. After the fifth pulse F, the signal C4 from the subsequent output of register 1.9 resets the address counter 1.6 and, through the first input of switch 1.4, enters the output of the last one and resets trigger 1.3 to the zero state, thereby blocking the passage of pulses of the clock 1.2 to counter 1.6 through the AND 1.5 element . The outputs of the register 10 in the initial conditions mode are in a high impedance state and do not affect other elements of the circuit. Next, a new address and new data are set, followed by a START pulse. The recording microcycle is repeated.

The result of the initial condition setting mode is the recording in all output registers of group 11 of data preceding the pseudo-random test and duplicated in the corresponding cells of the multi-bit memory unit 7. In the cells of block 1 of the single-bit memory, information is recorded corresponding to randomly selected outputs of the device, the signals on which change or not change in the pseudo-random testing cycle.

Additionally, in the specified mode, at the output of the device, any deterministic pre-calculated test can be transmitted from the data inputs 12. The START input 1 in this case functions as the synchronization input of the device.

The pseudo-random test generation mode is preceded by setting a single signal level at the input 16 and writing to the counter 1.1 in the control unit 1 a code determining the number of test words of the pseudo-random test. The number of test words is determined by the difference between the maximum counter code 1.1 and the initial code.

A short single pulse at the input 14 of the device START is set to trigger 1.3 in block 1 in a single state, which allows the passage of pulses from the output of the clock 1.2 through the first element And 1.5 to the input of the address counter 1.6. At the same time through the second element JMO And the named impulse comes through

the fourth output of the control unit 1 to the reset input of the register 3 and nullifies the last.

The mode timing diagrams to which the contents of the second bank of the memory element 1.8 correspond are shown in FIG. 2. By the signal, register 3 is put into shift mode and together with the parity element 2 forms a pseudo-random signal generator with zero initial conditions. The signal CSBD 1 fixes the outputs of the bus driver 5 in the high-impedance state and excludes the influence of the latter on the operation of the remaining circuit elements. On the leading edge of signal C1, the state of register 3 changes, at the outputs of which another pseudo-random code is generated, from which addresses are addressed to blocks 4 and 7, decoders 6 and 8. The contents of the read memory cell of block 4 are set at its output and is present during the microcycle of 6 clock cycles of signal F (CSRAM2 O, WRRAM2 1). The contents of a multi-bit cell are set at the outputs of block 7 after the second pulse F (Fig. 4) and fed to the first inputs of the adders modulo two groups 9, to the second inputs of which signals from the outputs of the decoder 8 are received. Moreover, if the decoder 8 has a gate input a single signal, then at all its outputs the signals are zero regardless of the signals at the other inputs; otherwise, a single signal determined by the input code is set at one of the outputs of the decoder. The result of modulo-two summing is an unchanged code of the first inputs at zero signals at all outputs of the decoder 8 or a code with one inverted bit, the position of which is determined by the output position of the decoder with a unit level. The summing result of the leading edge of C2 is written to register 10 and set at its outputs at CSRG 0, from where it is written to the previously addressed cell of block 7 and to the corresponding register of group 11, which can be written to by the code from the output of decoder 6. After the seventh pulse, signal C4 address counter 1.6 is reset to zero in control unit 1, and counter 1.1 increments its contents by one. Next, the following pseudo-random code is generated in register 3, and the microcycle is repeated until the counter 1.1 overflows, the signal from the overflow output of which through the second input of the switch 1.4 goes to the reset input of the trigger 1.3 and resets the last one. The passage of clock pulses from the clock through the AND element 1.5 is blocked. The pseudo-random test generation cycle is completed, which is indicated by the zero state of trigger 1.3.

Thus, in the proposed device, in addition to the properties inherent in the prototype device, it is possible to save on any arbitrarily selected outputs

0 fixed levels of logic signals in a pseudo-random testing cycle. A similar procedure is provided by recording single-bit memory of single signals in the cells of unit 4 at addresses corresponding to outputs with constant signal levels, which extends the functionality of the device; the nomenclature of objects of control, increases the productivity of the control and diagnostic equipment. The increase in productivity is due to a decrease in the number of deterministic tests that require a priori information about the structure of the control object, its operation logic, and components.

Claims (1)

SUMMARY OF THE INVENTION A device for generating tests comprising a pseudo-random sequence generator, a control unit, a first decoder, the information inputs of which are bitwise combined with the address inputs of a multi-bit memory block and connected to the corresponding bit outputs of the shift register, the inputs / outputs of the multi-bit block memory combined with the inputs of the group of output registers, the outputs of the register and the first inputs of the group of adders modulo two, the outputs of which are connected to the information inputs of the reg country, the second inputs of the adder group modulo two are connected to the outputs of the second decoder whose information inputs are connected to the outputs of the shift register, the resolution inputs 5 records of the group of output registers are connected to the corresponding outputs of the first decoder, characterized in that, in order to expand the functionality by storing at randomly selected outputs of the device fixed levels of logical signals in a pseudo-random testing cycle, a single-bit memory block, addressable the inputs of which are connected to the address inputs of the multi-bit memory block and the information inputs of the second decoder, the gating input of which is connected to the output single-bit memory block house, and bus driver, outputs 71800458 8 whose bit is combined with the input-registers, the inputs of the bus drivers / outputs of the multi-bit memory block are compatible with the information input of the unit: the outputs of the control unit from the first so far single-bit memory are inputs – eleventh are connected to the control input the initial data of the device, laziness is the shift register operating mode, k5 address inputs of which are the inverter bus sampling input, shift register information inputs, shift register synchronization input, control unit start is with the input to the input of the reset of the shift register, to the input of the device’s output, the input of the logical condition of the break of the multi-bit memory block, to the control input block is connected to the input of the read / write task of the multi-bit block 10 of the device operation mode, the inputs for - a memory, to a sample input block of a one-bit block of the duration of the formed memory cycle, a read / write input of a unit-test block of a device is a group of inputs of a bit memory, to a sample input of a control block, test outputs of a register; to the synchronization input of the device register are the outputs of the group; to the synchronization inputs of the group of output 15 registers. .Jr g 1.2 (G 8 : 1 8 V Rb 17 START 14 CSBD C1 CSRAM I WRHAM1 CSRAM; WRRAM; Control unit CSR6 C2 1 SZ J  17 The needle RB cs I SP 00 11.p f-nr. 1 PPPЈPЈGHPP (Л V bj W X j T. -v i- And sz s 53 x. a Si D Kommersant It 3233;.; ig .- 8SJ7008L 1800458 12345 ... FIG. 3