SU1354195A1 - Device for checking digital units - Google Patents

Abstract

The invention relates to automation and computing and can be used to control nodes. The purpose of the invention is to increase speed by providing an organization of control between working time intervals in real time. The device contains a multiplexer, switch, final set decoder, reference signature decoder, prohibition element, three AND elements, OR-NOT element, pulse driver, two delay elements, OR element, pseudo-random sequence generator and signature-based analyzer. Reliability of equipment operability, as a rule, is provided by periodic test control, which complements the on-line hardware performance monitoring apparatus. Periodic test control requires specially organized software and imposes a compulsory structural and temporary change in the process of functioning of the main equipment of the system. In the present invention, the equipment operability is monitored during pauses between working intervals, without the need for special software or changing the timing diagram of the operation process. In addition, the completeness of the test with the help of built-in hardware tools,. T can be significantly more complete than the traditional software test checks. The use of the invention in the design of integrated circuits of the combinational type (for example, programmable logic arrays) allows you to create the element base for designing highly reliable and most important nodes of computer technology in which the use of false information for control is unacceptable. Thus, the proposed combiner with built-in control can be used as part of highly reliable systems that provide an increased level of reliability of the information provided. 2 Il. (L co-eld N CO D1

Description

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The invention relates to computing and can be used in highly reliable systems that provide an increased level of authenticity of the output information.

The purpose of the invention is to increase the speed by ensuring the organization of the monitoring process between working intervals in real time.

Figure 1 shows the block diagram of the device, figure 2 - timing charts of the device.

The device contains a controlled node 1, a multiplexer 2, a switch 3 with three states, a generator of 4 pseudo-random numbers, a signature analyzer 5, a decoder 6 of the final set, a prohibition element 7, elements AND 8-10, a decoder 11 of the reference signature, an element OR -NOT 12, pulse shaper 13, delay elements 14 and 15, OR element 16, operation mode setting input 17, information input 18, response sign output 19, error output 20, synchronization input 21, initial setup input 22.

The health of the node 1 is monitored during pauses between working intervals. For this purpose, multiplexer 2, switch 3 with three states is connected to node 1. The signal at input 17 identifies the operating mode and the health check mode. When zero is applied to input 17, input information from information input 18 goes to node 1, and output information via open switch 3 to output 19. When a unit is fed to input 17, the health monitoring mode of node 1 is implemented.

Generator 4 can produce specified binary sets that constitute the minimum complete test, and signature analyzer 5 detects a given set of vectors or error response matrices of the monitored node 1, due to the list of its faults.

The decoder 6 of the final set sets the moment of demand with a clock pulse through the prohibition element 7 and the AND 10 state element of the decoder 11 of the reference signature. A single pulse at output 20 indicates that the reference signature is not

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matches the actual signature generated by the test.

Element And 8 is intended to block the switching of genera- rator 4 and analyzer 5 by analyzer 5, the reaction of node 1 to the last test set after convolution.

Element And 9 fe mode of health control skips the clock pulses from the input 21 to the inputs of the element And 8 and element 7 of the ban.

The element OR-NO 12 is intended for the initial installation of the generator 4 and the analyzer 5. The initial installation is performed through the pulse generator 13 when a positive differential is detected at the input 22 or a polling pulse of the state of the decoder 11 of the reference structure, delayed by the pulse 14 pulse.

The delay element 15 and the OR element 16 perform the functions of a differentiated delay of the signal applied to the input 17. Moreover, they only delay the negative edge of this signal by the response time of node 1. This delay is required for. In addition, when switching from the health monitoring mode to the operating mode, allow the operation of the switch Z. only after the appearance at their inputs of the node 1 reaction to the first working set.

The device works as follows.

When the power supply is turned on, the generator 4 and the analyzer 5 through the driver 13 and the element SHI-HE 12 are reset. This ensures that it is impossible to perform a truncated test-test sequence and, therefore, a false alarm. The initial state for generator 4 is the first test set, and for the analyzer, the zero code.

In the operating mode (input signal 17 is zero), the device operates in the usual way — multiplexer 2 switches input input 18 to input 1 and input 3 data to switch 3 and output 1 from three states. 19. Element And 9 does not pass the clock pulses from the input 21 to the generator 4 and the analyzer 5.

With the arrival of the inhibitory potential (the signal input 17 is equal to one), multiplexer 2 switches the input of node 1

to the output of the generator 4, the switch 3 enters a high impedance state and the element AND 9 transmits clock pulses from the input 21 through the element 8 to the synchronous inputs of the generator 4 and the analyzer 5,

Next, the health monitoring mode starts, in which for each clock pulse the generator 4 prepares a feed to the input of node 1 of the next test set, and the analyzer 5 perceives the reaction of node 1 to the previous test set.

At the moment when generator 4 generates a final set, which always follows the last test set, analyzer 5 minimizes the response of node 1 to the last test set. The decoder 6 recognizes the final set and a low potential appears at its output, which blocks the passage of the next clock pulse through the element 8 to the clock inputs of the generator 4 and analyzer 5. At the same time, the low level of the signal at the output of the decoder 6 allows the passage of the next clock pulse through the element 7 of the prohibition on the input of the element 10. If there is a low potential at the output of the decoder 11 of the reference signature, then the node is operational, and low potential remains at the output 20. Otherwise (a malfunction occurred at the node), the signature is different from the reference one, and a single impulse appears at output 20, indicating the presence of a malfunction in the circuit.

A polling pulse of the state of the decoder 11 of the reference signature, delayed by the element 14 for the duration of the clock pulse, sets the oscillator 4 and the analyzer 5 to the initial state through the element OR-NOT 12, and the monitoring cycle is repeated.

Claims (1)

As a result, node 1 is monitored at intervals when it is idle. In this case, depending on the length of the pauses, the performance monitoring is carried out repeatedly in cycles or in quanta, each time continuing the test from the test set on which the last interruption was detected by the operating mode. Invention Formula A device for controlling digital nodes, containing a pseudo-random number generator, signature analysis5 0 mash, first delay element, switch, multiplexer, three AND elements, pulse shaper, characterized in that, in order to increase speed by providing an organization of control process between real-time working intervals, the device contains a final set decoder, a reference signature decoder, a prohibition element, an OR-NOT element, an OR element, a second delay element, the synchronous input device being connected 5 with the information input of the first element And, the output of which is connected to the information input of the second element And and the information input of the prohibition element, the output of which is connected to 0 by the control input of the third element I and through the first delay element with the first input of the element KG1I-NOT, the second input of which is connected to the output of the for- pulse generator, the input of which is connected to the input of the initial installation of the device, the output of the element OR is NOT connected to the resolution input of the pseudo-random number generator and the signature analyzer, the output of which is connected to the information input of the reference signature decoder, the output of which is connected to the information input of the third element AND whose output is the output of the trait 5 errors of the device, the input of the operation mode of which is connected to the control input of the first AND element, with the control input of the multiplexer to the first input of the OR element and through 0 the second delay element with the second input element OR, the output of which is connected to the control input of the switch, the output of which is the output of the device response sign, the information input of which is connected to the first information input of the multiplexer, the output of which is connected to the output of the device for connection to the inputs of the monitored node, the information input of the switch is the input of the device for connection to the output of the monitored node and is connected to the information input of the signature analyzer, the input is blue ronizatsii 5 of which is connected to the output of the second element And and the synchronization input of the pseudo-random number generator, the output of which is connected to the second information input of the multiplexer and infor 13541956 by the decoding input by the finite control inputs of the second element go. set, the output of which is connected to the AND and the element of the ban.