RU1774380C - Device for checking multibit memory blocks - Google Patents

Abstract

The invention relates to computer technology and can be used for functional control of blocks of multi-bit random access memory. The aim of the invention is to increase the speed, increase the reliability of the control device. The device contains an OR-NOT element 1, AND elements 2-6, a pseudo-random sequence generator 7, a switch 8, a verifiable random access memory block 9, a register 10, a generator 11, triggers 12 and 13, a delay element 14, a comparison unit 15 , first 16, second 17, third 18 and fourth 19 inputs of the device mode setting, the signal output of the device 20, the second 21 and the first 22 groups of inverters, the fifth 23 input of the setting of the device mode, information input 24, element NOT 25, address outputs 26 of the device , output 27 write / read device information s device 28 outputs, AND-NO element 30, first 31 and second 32 registers. The device allows for functional control of random access memory blocks on the signature test sequence, and therefore, to increase the reliability of the control of the device. 2 tablets, 2 sludge, 26 with С XI XJ N СО 00 о

Description

Fig. /

The invention relates to computer technology and can be used for functional control of random access memory blocks.

A device for controlling RAM is known, which allows monitoring the memory and, as a result of the control, form it on the signature analyzer 1. The disadvantage of this device is that before the control it is necessary to calculate the reference signature, as well as the fact that during the control the address change sequentially, which leads to low reliability of the control. The closest technical solution to the invention is a device for monitoring RAM blocks, comprising a generator, counter, decoder, AND elements, a switch, a trigger, a delay element, a signature analyzer, a group of inverters 2. The device allows monitoring the RAM blocks, and Result control shaper using a signature analyzer. The disadvantages of the prototype, as well as the analog device, are the need to know the reference signature before the control, as well as the low reliability of the control, since the address change in it is carried out sequentially.

The aim of the invention is to increase the reliability of control and increase the speed of the device.

The goal is achieved in that in a device for monitoring random access memory blocks containing a trigger, a switch, a delay element, the first and second elements. And, the first group of inverters, and the outputs of the switches are the address outputs of the device, the outputs of the first group of inverters are the information outputs of the device, the pseudo-random sequence generator, the second trigger, the third, fourth and fifth elements AND, the AND element, the second group of inverters , the element is NOT, a comparison unit, a register whose outputs are connected to the first group of inputs of the comparison unit and to the first group of inputs of the second group of inverters, the output of which is connected to the second group of inputs of the switch, the outputs of which are connected to the address outputs of the device, while the write / read output of the device is connected to the control input of the switch, the second input of the third element And, the direct output of the first trigger, the synchronization input of which is connected to the output of the second element And, the third input of which is connected to the inverse output of the first trigger, the second input of the second element AND is connected to the output of the inverter, the input of which is connected to the first input of the third element I. synchronization inputs of the pseudo-random sequence generator, input the synchronization odes of the first and second registers and the output of the first AND element, the outputs of the pseudo-random sequence generator are connected respectively to the information inputs of the second register, the outputs of which are connected to the information inputs of the first register, the inputs of the AND gate, the first group of inputs of the first group of inverters, the outputs which are connected to the second group of inputs of the comparison unit and are the information inputs of the device, the information inputs of the register are the information inputs of the first group of the device, the input of the register synchronization is connected to the output of the delay element, the input of which is connected to the output of the third AND element, the output of the AND gate is NOT connected to the installation input to the pseudo-random sequence generator unit, the outputs of the first register are connected to the first group of switch inputs and the group of inputs of the first element AND, information inputs of the pseudo-random sequence generator

0 are information inputs of the device, the output of the comparison unit is connected to the first input of the fourth element And, the output of which is the signal output of the device, the second input of the fourth element is 5 And connected to the inverse output of the second trigger, the unit inputs and the zero of the second trigger are respectively the third and fourth input of the device mode reference, the generator output is connected to the first input of the first AND element, the second input of which is connected to the generator input and to the direct output of the second trigger, the first th input of the second AND gate connected to the output of the fifth AND gate and

5 by the second input of the OR-NOT element, the first input of which is the fifth input of the device mode setting, the output of the OR-NOT element is connected to the zero input of the second register, the input of the initial state of the pseudo-random sequence generator is the second input of the mode reference devices. In comparison with the prototype, the proposed technical solution has distinctive features and meets the criteria of the invention of novelty.

The introduction of the indicated blocks with the corresponding connections into the known device makes it possible to increase the reliability of the control of random multi-bit memory blocks by generating arbitrary address and information sequences during monitoring, as well as to eliminate the stage of generating reference signatures during memory monitoring. Thus, it can be concluded that the proposed device meets the criteria of the invention, significant differences.

Fig. 1 is a functional diagram of a device for monitoring random-access memory blocks; figure 2 is a functional diagram of a group of inverters; Fig. 3 is a functional diagram of a pseudo-random sequence generator.

Figure 1-3 shows the element OR NOT 1, elements AND 2-6, pseudo-random sequence generator 7, switch 8, verifiable random access memory block 9, register 10, generator 11, triggers 12 and 13, element 14 delays, comparison unit 15, first 16, second 17, third 18 and fourth 19 inputs of the device mode setting, signal output 20 of the device, first 22 and second 21 groups of inverters, fifth 23 input of the device mode setting, information input 24, element NOT 25 , address outputs 26 of the device, output 27 write / read devices, information outputs There are 28 devices, AND-NOT element 30, first 31 and second 32 registers, adders 33-35 modulo two, inputs 36-39 of the inverter group, outputs 40-42 of the inverter group, adder 43 modulo two, register 44. outputs 45 -47 pseudo-random sequence generator, inputs 48-51 of the pseudo-random sequence generator.

A device for monitoring random-access memory blocks (Fig. 1) contains a switch 8, a first trigger 13, a delay element 14, a first 2 and a second 3 And elements, a first group of 22 inverters, a pseudo-random sequence generator 7, a second 12 trigger, and a third 4 , the fourth 5th and fifth 6th elements AND, the AND-NOT element 30, the second group of 21 inverters, the HE 25 element, the comparison unit 15, the register 10, the outputs of which are connected to the first group of inputs of the comparison unit 15 and the first group of inputs of the second group 21 inverters. The output of the latter is connected to the second group of inputs of the switch 8. the outputs of which are connected to the address outputs 26 of the device. The write / read output 27 of the device is connected to the control input of the switch 8, the second input of the third element And 4, the direct output of the first trigger 13, the synchronization input of which is connected to the output of the second element And 3. The third input of the element And 3 is connected to the inverse output of the first trigger 13 The second input of the second element And 3 is connected to the output of the inverter, the input of which is connected to the first input of the third element And 4, the synchronization inputs of the generator 7 of the pseudo-random sequence, the first 31 and second 32 registers and the output of the first element nta And 2. The outputs of the generator 7 of the pseudo-random sequence are connected

0, respectively, with the information inputs of the second register 32. the outputs of which are connected to the information inputs of the first register 31 inputs of the AND-NOT 30 element, with the first group of inputs of the first

5 groups of 22 inverters. The outputs of the latter are connected to the second group of inputs of the comparison unit 15 and are information inputs of the device 28. The information inputs 29 of register 10 are

0 information inputs 29 of the first group of the device. The synchronization input of the register 10 is connected to the output of the delay element 14, the input of which is connected to the output of the third element And 4. The output of the element

5 AND-NOT 30 is connected to the input of the installation in the unit of the generator 7 of the pseudo-random sequence. The outputs of the first register 31 are connected to the first group of inputs of the switch 8 and the group of inputs of the fifth

0 of AND element 6. The information inputs of the pseudo-random sequence generator 7 are the information inputs of the device 24. The output of the comparison unit 15 is connected to the first input of the fourth element AND 5, the output of which is the signal output 20 of the device. The second input of the fourth element And 5 is connected to the inverse output of the second trigger 12. The installation inputs of one and zero of the second trigger 12 are the third 18 and fourth 19 respectively of the device mode setting input. The output of the generator 11 is connected to the first input of the first element And 2, the second input of which is connected to

5 by the input of the generator 11 and with the direct output of the second trigger 12. The first input of the second element And 3 is connected to the output of the fifth element And 6 and the second input of the element OR NOT 1, the first input of which is

0 by the fifth input 23 of the device mode setting. The output of the OR-NOT element is connected to the zero input of the second register 32. The input of the installation to the initial state of the pseudo-random sequence generator 7 is the second input 17 of the device mode setting.

The device operates as follows.

It should be noted that the feedback polynomials of generator 7 are nth degree polynomials belonging to the maximal exponent. This means that all nonzero output sequences have a period of 2n-1 (the n-bit of the register used in the generator). Such a generator is a generator of a maximum period (see AP Gorshko, Synthesis of Diagnostic Circuits of Computing Devices. - M.: Nauka, 1987, p. 288).

Before starting work, the value of code N is written to the generator 7 (all units 1, taking into account the feedback polynomial). A polarity positive pulse is applied to input 23, which resets the contents of register 32.

Logic O is supplied to input 16. This means that the control of the memory unit 9 is carried out with direct data values. Register 10 is set to logical O at its outputs, and trigger 13 is set to logical O at its direct output (the initial setup circuits for register and trigger 13 are not shown). Fig. 1 also does not show a signal of access to the tested block of random access memory, since this signal does not affect the achievement of a positive effect.

Upon receipt of logic O signal at input 18, and logic 1 signal 19 from generator 11 through the first AND element 2, clock pulses arrive at the inputs of generator 7 and registers 31 and 32. Thus, enumeration of all states of the generator 7 with the maximum period begins. The trigger 13 is set to logical O, which determines the mode of recording information in the checked memory unit 9. Table 1 shows a possible example of changing the addresses and information that enter block 9 for a three-bit pseudo-random sequence generator.

It can be seen from Table 1 that information (011) is written to the address (000), i.e. address of the next cell of memory unit 9, etc. With all units at the outputs of the register 32, an AND-NOT 30 element is triggered, which sets the generator 7 to the state of all units at its outputs, which prepares the generator 7 for the mode of reading information from the memory unit 9. With the value of all units at the outputs of the register 31, the And element 6 is triggered, which nullifies the register 32, preparing it for reading and closing the chain of addresses and data to check the memory unit 9. The operation of the element And 6 also leads to the fact that the clock pulses from the generator 11 switch the trigger 13 to a single state at its direct output.

The read mode from the memory unit 9 begins.

In read mode, at the address specified by register 10, information is read that is written to the same register. Since the register 10 is initially set to a logical state O at its outputs, information (011) is read (see table 1). Further, at the address (011), it reads (001), etc. Thus, the loopback mode of the random access memory block 9 is implemented.

When entering the input 19 logical O, and the input 18-logical 1 on the direct

On output 5 of trigger 12, logical O is set, which means the end of the memory block check. A trigger 1 is set at the inverse output of trigger 12, which enables content comparison

0 of register 10 and register 32, which operates synchronously with register 10. If the contents of register 10 and the contents of register 32 are equal, then the memory block 9 is working correctly, otherwise the memory block failed5 is equal.

The second monitoring step is to check the memory unit 9 with inverse data values. To this end, logic 1 is supplied to input 16. Installing triggers,

0 of the generator 7, registers 31, 32, is implemented in the same way as in the previous case, except that the register 10 is set to logic 1 at its outputs.

5 Table 2 shows a possible example of changing addresses and information received in the memory unit 9 during monitoring.

The advantages of the proposed device for controlling blocks of random access memory can include the following.

A pseudo-random enumeration of addresses and data is carried out during writing and reading, which leads to a higher

5 reliability control in comparison with the known device. In this case, the feedbacks of the registers that are used in the generator 7 can be set arbitrarily, which provides various test

0 sequences used for control.

Checked memory zero cell.

When controlling blocks of the operational memory, there is no need to know the reference signature; the number of readings each time can be arbitrary.

The inventive device can be used to control the blocks of random access memory

Reliability of the control can be enhanced by using a generator with various feedback polynomials. The technical and economic advantage of the claimed device compared to the known one consists in increasing the reliability of the control by forming arbitrary address and information sequences, as well as in eliminating the stage of forming the reference signature during the control.

Claims (1)

SUMMARY OF THE INVENTION A device for monitoring random-access memory blocks, comprising a switch, first and second triggers, a delay element, a generator, first to fifth elements AND, two groups of inverters, an element NOT, a pseudo-random sequence generator, a comparison unit, a first register; the outputs of which are connected to the inputs of the first group of the comparison unit, the inputs of the second group of which are connected to the outputs of the inverters of the second group, the synchronization input of the first register is connected to the output of the delay element; connected to the output of the third element And, the first input of which is connected to the output of the first element And and the synchronization input of the pseudo-random sequence generator, the inputs of the initial installation group of which are the inputs of the device mode task group, the second input of the third element And is connected to the control input of the switch , the direct output of the second trigger and is the write-read output of the device, the inverse output of the second tripere is connected to the third input of the second element And, the direct output of the first trigger connected to the second input of the first element And, the first input of which is connected to the output of the generator, the input of which is connected to the direct output of the first trigger, the inputs of which are 1 and O are the second, second and third inputs of the device mode reference, respectively, the task input the pseudo-random sequence generator mode is the first input of the device mode setting, the inverse output of the first trigger is connected to the second input of the fourth element And, the first input of which is connected to the 5 output of the comparison unit, the output of the fourth the AND element is the signal output of the device, the outputs of the inverters of the first group are connected to the information inputs of the second group of the switch, the outputs of which are the address outputs of the device, the information inputs of the first register are the information inputs of the device, the output of the fifth element is connected to the first input of the second ment And, the output of which is connected to the synchronization input of the second trigger, characterized in that, in order to increase the speed of the device and increase the reliability of control due to without any constant faults, the second and third registers are entered into it, the OR-NOT element and the AND-NOT element, the output of which is connected to the unit input to the pseudo-random sequence generator unit 5, the inputs of the AND-NOT element are connected to the outputs of the third register, information the inputs of the second register and the inputs of the group of inverters of the second group, the control inputs of the inverters 0 of the first and second groups are combined and are the fourth input of the device mode setting, the synchronization inputs of the second and third registers are combined and connected to the output of the first element And, the outputs 5 of the second register are connected to the inputs of the fifth AND element and to the information inputs of the first group of the switch, the output of the fifth AND element is connected to the second input of the OR-NOT element, the first input of which is the fifth input of the device mode setting, the output of the OR-H element E is connected to the input of the installation in O of the third register, the outputs of the first register are connected to the inputs of the inverter group 5 of the first group, the output of the first element AND is connected to the input of the element NOT, the output of which is connected to the second input of the second element I. fifty Table 1 361 37 - 53 38 34 41 39 Ji -. Continuation of the table, 1 table 2 ABOUT 45 .6  1