SU1529293A1 - Device for shaping test sequence - Google Patents

Abstract

The invention relates to computing and can be used in hardware monitoring devices of operational memory. The device contains triggers 2, 3, elements AND 4-7, multiplexers 9-11, address counter 12, cycle counter 13, control counter 14, control block 15, AND element 19 with corresponding functional connections. The device significantly reduces the monitoring time of the RAM blocks, because the whole monitoring mode consists of two modes: the recording mode of reference signals and the reading and comparing mode. 2 Il.

Description

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iiiij element and 19 with corresponding functional connections. The device significantly reduces the time control blocks operative we, because the whole

 The invention relates to a computing technique and can be used in the control of operational memory devices.

The purpose of the invention is to improve the speed of the device.

ila FIG. 1 is a diagram of an apparatus for generating a test sequence; Figure 2 shows an example of the implementation of counters. .

The device (Fig. 1) contains an input of 1 start, the first 2 and second 3 trigger N, the first 4, the second 5, the third 6, and the fourth 7 elements AND, the input 8 si-hrsn5; the first 9, the second 10 and the third 11 multiplexers, the counter 12, the address 5, the counter 13 cycles, the control counter 14, the control unit 15, the output-write-read 16 and the end of the test 17, the address outputs 18, p | th element And 19, the fourth multi - | Plexor 20, -information outputs 121 and output 22 circulation. I Counters 12-14 (Fig. 2) can. ; be implemented on the element And 23, {register 24 and the adder 25. I The device works as follows |

 Before the start of the control, the triggers and 3 and the counters 12-14 are set-: go to the zero position (the input of the initial setup in Fig. 1 is not activated), at the input;, e 1. There is a logical zero. When a start signal is received at input 1, the passage of clock pulses from the input of 8 hrs is allowed: cut the AND 4 element to output 22 of the device. This signal is a signal to access a monitored memory block.

The control unit 15 is a combinational unit, executed, for example, on the CTM., The unit 15 at its outputs decides the following logical

equations. .

 YJ X2-X1 + X2 (X8 (X3SX6) + X5 (OOHb) ФХ8 Х + Х2-Х1 (Х5 Х8 + Х5 (ХЗ®Х6; + Х8 (ХЗ®Х6)); (

iY2 Х1 + (ХЗ®Х6) + (Х5®ХВ) Y3 Х1Х7;

(2) U)

The monitoring mode consists of two modes: the recording mode of the reference signals and the reading and comparing mode. 2, il.

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Y4 XI + (X5WX8) CHCSahb); (4) Y5 Х1Х2-ХЗ-Х7. (5)

Since at the initial moment of time all arguments are equal to zero, the following potentials will be set at the output of block 15:,,,,. .

The zero value Y1 provides the switch to the output of the multiplexer 11 code out of n units 11 ... 1, where n is the size of the monitored RAM.

A single value of Y2 allows the addition of one to the counter 12 of the address. The zero value of Y3 prohibits the addition of one to the contents of the counter 14. A single value of Y4 provides the generation of a recording feature for the monitored RAM. I. . The zero value of the signal Y5 indicates that the test has not yet ended. Consequently, on the first clock signal, the device generates a signal to access output 22 to a monitored memory block, generates a zero address at outputs 18, a sign of writing at output 16 and a single value of control information at outputs 21. On the second clock pulse, the device will receive the first address, record sign and single value of the recorded information. Since the state of counter 14 does not change (the zero signal at the input of V), then at the output of multiplexer 9 there is a zero value of the transfer signal from the higher bit, the counter 12 of the address. After all the cells of the monitored block are painted with a single background, the output of multiplexer 9 is an overflow signal, which, having passed through multiplexer 20, allows +1 to be added to the contents of counter 13 and is set to the first clock pulse at the output of counter 13 code 01. At the same time,, Y3 1 ,,,.

fantipcop 11 under the action of the signal; 1l provides a connection to the input of the comparison circuit (in FIG. 1

not shown) of the signal of logical units; the second input receives the read signal from the monitored memory block. Since, the readout sign arrives at the Jixofl of the memory unit, and the signal allows the output signal of the device to be compared. The single signal Y3 provides the removal of the signal to prohibit the counting to the counter 14. As a result, under the action of the clock signal, the counter 14 sets them to the single state, after which, in accordance with equation (3), Y3 will become zero, since the signal X7 will become zero, due to the fact that the counter 12 is set to the zero state by this clock pulse. Thus, Y1, Y2, Y3, Y4 and Y5 will not change until counter 12 has counted to half its capacity.

Regardless of the counter size, the described process will continue unchanged until the penultimate bit is set to one. At the same time, a single signal () appears at the output of the multiplexer 10. This results in Y2 becoming equal to unity,,,. In this case, the device from the read mode enters the write mode, the multiplexer 11 passes the code 00 to the output.

Following the clock pulse, code 00 will be recorded in the monitored memory block at address 1. The next clock pulse will set trigger 1 into unit. At the same time, the following values will be set at the outputs of control unit 15:,,,. On the next clock pulse, counter 12 changes its state (trigger 3 is reset to zero at the counting input) and the device will read and compare data with zero. The next clock signal will set the trigger .3 to one and the device will operate as described.

The operation of the device will continue until the painting of the entire RAM controlled by inverse codes is completed. After the completion of the painting of the monitored RAM, the counter-12 of the address is overfilled, the signal that passes through the AND 19 element and the multiplexer 20 is resolved, will allow the addition of +1 to

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unit 15 will be set to the following codes:,,,,. The next clock pulse on the counter 13 will be set to code 10, on the counter 14 - code 1, At the same time, the transfer from (nl) -ro bit of the counter 12 is addressed to the output of the multiplexer 9 (n is the number of counter bits), and at the output of multiplexer 1.0 - (, n-1) -th digit of the counter. At the output of the control unit 15, the following values will be set. ,,,, The operation of the device will proceed in the same way as described until the signal at the output of multiplexer 10 takes a single value, which means that until the device checks 1/4 of all the cells of the monitored memory block, i.e. until it is set to one (n-1) -th bit of the counter 12 address. The control unit 15 will set codes on its outputs:,,,,.

The next clock impulse device at the address () will record zero. After that, with another clock pulse, trigger 3 will be set to a single value, and thus the output of block 15 will be provided with the following values:,,,. Thus, the next clock pulse will read the information from the address 2, and then the information inverse to the recorded one will be entered at the same address, since the signal Y1 will take a single value. The process will continue until trigger 2 is set to a single value. The installation of trigger 2 will occur when the signal at the output of multiplexer 9 and. In this case, the clock pulse trigger 2 switches to state 1 and will remain in this state until the end of the test, since the zero value of the signal at the second input of element And 5 from the zero output of trigger 2 sets a zero potential on the D input;

After the RAM verification process (with the initial painting by units) is finished, the transfer from the high bit of counter 12, which through element 19 goes to the single input of multiplexer 20 and then to the counter enable input, is finished.

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13. Sequences when the next clock pulse arrives.

In state 1, the second transfer is carried out from the high bit of counter 12 and code 13 is set at counter 13. In this case, the device will transfer to PC mode by spacing the RAM controlled by the background of zeros,,,,, t. e. before the overflow of the counter 12, the overflow signal will indicate the end of the list of RAM-controlled background of zeros.

Further, the process will proceed as follows) KOj as described, with the only difference that code 11 will be installed on counter 13. The monitoring process will continue until code from n units 1 ... 1 is set on counter 14 and the fourth transfer from counter 12. A single value Yb will indicate the end of the test, after which the start signal is taken at input 1. The start signal is also removed when an error is detected (not shown in Fig. 1).

Claims (1)

Invention Formula A device for generating a test sequence containing a control unit, a trigger, an address counter, the low-order outputs of which are device address outputs and connected to the information inputs of the second multiplexer, a control counter whose outputs are connected to the control; the inputs of the first and second multiplexers , the third one, which differs from the fact that, in order to improve performance, the elements are introduced into the device And from the first to the fifth, the loop counter, the fourth multiplexer, the counting trigger The inputs of the first element I are the start and synchronization inputs of the device, the output of the first element I is the output of the start of the cycle of the device and is connected to the synchronization of the address counter, control counter and cycle counter, and the synchronization counter with the second inlet-1 92938 the house of the third element And, the first input of which is connected to the fourth input of the control unit and to the output of the first multiplexer, whose information inputs are connected to the outputs of the lower bits, the address counter, the overflow output of which is connected to the seventh input of the control unit, 4 PIA, inverse of the second And element, the first input of the fifth element And and to the first information input of the fourth multiplexer, the second information input, the control, the main input and the output of which are connected respectively to the overflow output account cycle loop, the output of the fifth element And and with the control input of the cycle counter, the outputs of which connected to the first and second inputs of the control unit whose third input is connected to the second input of the fifth And element and to the output of the fourth And element, the cohort inputs are connected to the outputs of the control counter, the control input of which is connected to the third output of the control unit, the first output which is connected to the control input of the third multiplexer, informational inputs of the first and second groups of which are the direct and inverse reference data of the device, and the outputs are informational outputs of the device, the second output of the control unit is connected to the control output of the address counter and the fourth input of the third element And, the third input connected to the output of the second multiplexer and to the fifth input of the control unit, the sixth and eighth inputs of which are connected to the direct outputs of the corresponding counting trigger and the trigger, the inverse output of which a connected to the direct input of the second AND gate, whose output is connected to the data input of the flip-flop, whose clock terminal is connected to the inverse output of the third AND gate, the fourth and fifth outputs of the control unit are respectively read and write outputs konp.a verification device. Fm.g