SU1283858A1 - Device for checking memory blocks - Google Patents

Abstract

The invention relates to computing and can be used in the equipment controlling the operation of memory devices. The purpose of the invention is to increase the reliability of the device. The device contains three multiplexers, an ip-random signal generator, two shift registers, a comparison unit, a counter, and a control unit. The control of the memory block consists in sequential recording of each address of the codes generated with the help of a pseudo-random signal generator, followed by their reading and comparison. 2 Il. (L

Description

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The invention relates to computing and can be used in the equipment controlling the operation of memory devices.

The purpose of the invention is to increase the reliability of the device.

Fig. 1 shows a block diagram of a device for monitoring memory blocks; Fig. 2 is a block diagram of the control unit.

A device for controlling memory blocks contains a control block 1, the first 2, the second 3 and the third 4 multiplexers, 5 pseudo-random generator

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multiplexer 4 connects generator

5k to the input of the sequential write register 7.

Thus, at the first address in the memory block 15 some random code from register 6 will be written. Then, by the signal from the output 12 of the control unit 1 - LEN, the contents of the counter 9 are increased by one, and by the signal from the output 13 of the control unit 1 in the register

6 a cyclic shift of one bit occurs, the lower half of register 7 records logical 1 or logical O from generator 5. When

signals, the first 6 and the second 7 regnet-f5 are the contents of the highest bit of the

multiplexer 4 connects generator

5k to the input of the sequential write register 7.

Thus, at the first address in the memory block 15 some random code from register 6 will be written. Then, by the signal from the output 12 of the control unit 1 - LEN, the contents of the counter 9 are increased by one, and by the signal from the output 13 of the control unit 1 in the register

6 a cyclic shift of one bit occurs, the lower half of register 7 records logical 1 or logical O from generator 5. When

shift shells, block 8 comparisons and counter 9.

Control unit 1 has outputs 10-1.4.

The device is connected to a memory unit 1520.

The control unit 1 contains a master pulse generator 16, the output of which is connected to the input of the frequency divider 17 and the input of the delay element 18, the frequency divider 19, is connected, 51st with the output of the divider 17 and one of the inputs of the AND element 20, the other input of which is connected to the output He element 21, the output of the divider 19 is also connected to one of the inputs of the element 22. Through the button 23, the reset input 24 to the zero of the divider 17 and the reset input 25 to the single state of the divider 19 of the sub-register 7 is lost. In memory block 15, the code from register 6 is written to the second address. In this sequence, the first k addresses are filled in,

The k + 1-th signal from the output 12 of the control unit 1 records in the counter 9 k + 1-st address,

At the output of the divider 17 of block 1, a signal of a logical unit appears, 25 At the output 10 of block 1, a logical 1 is formed. From this signal,

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the higher bit of register 7 through multiplexer 4 is connected to the serial write input of this register, and the serial record input of register 6 is connected to the output of generator 5 via multiplexer 3. A new random code was written to the 7 leading clock cycles, keys to the bus 26 of zero potential. It is recorded at the k + 1 address in the device for monitoring blocks of memory block 15. At the k + 2 address, the deputy works as follows,

Before starting the test, by pressing button 23, the input 24 of the divider 17 and the input 25 of the divider 19 are given a logical zero signal and the output of the divider 17 is set to a logical zero and the output of the divider 19 is a logical one,

The signal from the output 12 of the unit 1 into the counter 9 is entered into the first address. From the outputs of the counter 9, the parallel code arrives at the address inputs of the monitored memory unit 15. Signal

logical unit with output 11 block 50 reading mode. Output signal

As 1 memory block 15 is transferred to re-12 of block 1 into counter 9, it is recorded pergem records. At output 10 of block 1, the pack address. At the output of divider 17 of the board, a logical zero signal of logical zero is formed. This signal on this signal multiplexer 2 base output of the high bit of the register 6

switches the outputs of register 6 to the information multiplexer 3 55 with

the memory inputs of the memory block 15, the multi-input of the sequential write

Tiplexer 3 connects the high register output. On the front of the output signal

register bit 6 with the input of the last-14 block 1 is produced parallel

recording of this register, and writing k-bit code from the outputs

gistra 7 is lost. In memory block 15, the code from register 6 is written to the second address. In this sequence, the first k addresses are filled in,

The k + 1-th signal from the output 12 of the control unit 1 records in the counter 9 k + 1-st address,

At the output of the divider 17 of block 1, a signal of a logical unit appears. At the output 10 of block 1, a logical 1 is generated. From this signal, the output

the shifted register code 7 is written one digit, i.e., every k cycles of operation register 6 and 7 are swapped: when odn. is filled, in the other there are cyclic shifts and writing codes from it into memory block 15 and vice versa. The write operation is continued until the memory block 15 is completely filled. After the end of the recording, a logical zero signal appears at the output of the divider 19, and this signal from the output 11 of block 1 transfers 15 fleets of memory

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Claims (1)

Invention Formula A device for controlling memory blocks, containing the first multiplexer, the output of which is the information output of the device, the control unit, the first output of which is connected to the control input of the first multiplexer, and the second is the control output of the device, counts. chick whose input is connected to the tre O 5 0 five The control unit's output, the comparison unit, one of the inputs of which are informational inputs of the device, and the output of the comparison unit is in the control output of the device, a pseudo-random signal generator, characterized in that, in order to increase the reliability of the device, the first and second shift registers and the second. and the third multiplexers, with the control inputs of the second and third multiplexers connected to the first output of the control unit, the fourth output of which is connected to the control input of the second the shift register and the first control input of the first shift register, the second control input of which is connected to the fifth output of the control unit, the output of the pseudo-random number generator is connected to the first information inputs of the second and third multiplexers, the second information inputs of which are connected respectively to one of the outputs of the first and the second shift registers, the serial write inputs of which are connected respectively to the outputs of the second and third multiplexers, the input of the parallel record of the first register shear connected to data input device, the first shift register output is connected to the other inputs of the comparing unit, the first multiplexer data inputs connected to outputs of the shift registers, the counter output is the address output of the apparatus. five 0 F // Editor A, Revin Compiled by V. Rudakov Tehred A. Kravchuk Order 7А50 / 52 Circulation 589, Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 (PtiZ.2 K pp e who p to simishin e c