SU1138799A1 - Device for generating test sequences - Google Patents

Abstract

A device for generating test sequences, containing a clock generator, a cumulative register, a trigger and the first element, And, and the input of the clock generator is the device start input, the output of the cumulative register is the output of the device, characterized by A shift register, a comparison circuit, a counter, an OR element, a second, a third, a fourth and a fifth AND elements are entered into the device, with the first output of the clock generator connected to the control The first input of the comparison circuit, the first and second information inputs of which are connected respectively to the output of the counter and the first output of the shift register, the second output of which is connected to the information input of the cumulative register, the input of the shift and the recording resolution of which are connected respectively to the outputs of the fourth and fifth elements And, the first inputs of the fourth and fifth elements And are connected respectively to the second and first outputs of the clock generator, the second inputs of the fourth and fifth elements And are connected to the unit with the trigger output, the zero output of which is connected to the first input of the first element And, the second input of which is connected to the single input of the trigger and the comparison output of the comparison circuit, the output of which is compared to the OR input, the second input of which is connected to the output of the first element AND, the output of the OR element is connected to the first input of the third element AND, the second input of which is connected with the third output of the clock generator, the output of the third element AND is connected by the t input of the shift register writing input, The shift of which is associated with the second output of the clock COCO pulse generator, the reset inputs of the shift register and the counter are input to the initial setup of the device, the information input of the shift register f is connected to the output of the counter, the counting input of which is connected to the output of the second element I, the first and second inputs of which are connected respectively to the fourth output of the clock pulse generator and the first input of the third element I.

Description

The invention relates to computing and can be used to monitor and diagnose logical circuits. Devices for generating pseudo-random binary sequences are known that allow a large number of mismatched binary sets to be generated from h bits. In these devices, each successive bit of a sequence is determined by the value of a logic function from some previously formed bits of the same sequence. The choice rule for these bits is based on the properties of indecomposable polynomials of degree n. The devices include an h-bit shift register with modulo 2 adder. in the feedback circuit, Cl3 and 2. The disadvantage of these devices is the difficulty in organizing complete enumerations of zeroes and ones in h rows. For different / n, the combination of bits for which the next bit of the sequence is generated is required. This limits the functionality of the devices. The closest technical solution to the proposed device is a test sequence generator, which includes a cumulative register having a shift circuit, the output of which is the output of the device, a trigger, the AND element and a clock generator, the input of which is the input of the device. The test sequence is generated in the device by accumulating it on a cumulative register of 2 + (| 1-1) bits by connecting one bit each, the value of which is determined by the state of the memory cell of 2 bits at the address corresponding to and -1 of the preceding sequence bits. The resulting test sequence contains all possible combinations of n zeros and SzZ units. In the known device, the amount of equipment doubles with increasing n by one, which limits the length of the generated sequence to small ones. The aim of the invention is to expand the scope. The goal is achieved by the fact that the device for generating test pulses, containing a clock generator, a storage device, a register, a trigger and a first element, And, the input of the generator of clock pulses is the device start input, the output of the storage register is the device output , a shift register, a comparison circuit, a counter, an OR element, a second, a third, a fourth and a fifth AND elements are entered, the first output of the clock generator is connected to the control input of the comparison circuit, the first and second inf The memory inputs of which are connected respectively to the output of the counter and the first output of the shift register, the second output of which is connected to the information input of the cumulative register, the input of the shift and the recording resolution of which are connected respectively to the outputs of the fourth and fifth elements and the first inputs of the fourth and fifth elements And they are connected respectively to the second and first outputs of the clock, the second inputs of the fourth and fifth elements And are associated with a single trigger output, zero output of which is Linked to the first input of the first element AND, the second input of which is connected to the single trigger input and the comparison output of the comparison circuit, the non-comparison output of which is connected to the first input of the element whose second input is connected to the output of the first AND element, the output of the OR element is connected to the first input of the third element And, the second input of which is connected with the third output of the clock, the output of the third element And with the input of the write resolution of the shift register, the shift input of which is connected with the second output of the clock pulse generator All the inputs for the reset of the shift register and the counter are the input of the initial setup of the device, the information input of the shift register is connected to the output of the counter, the counting input of which is connected to the output of the second element And, the first and second inputs of which are connected respectively to the fourth output of the clock generator and the first the input of the third element I. FIG. 1 shows a block diagram of a device for generating test sequences; 2 a temporal diagram of the operation of the device. The device contains a clock pulse generator 1, a counter 2, a shift register 3, a comparison circuit 4, a trigger 5, a first 6, a second 7, a third 8, a fourth 9, and the fifth TO elements AND, the OR element 1-1 and a cumulative register 12, input 13 initial installation and launch input 14, the device operates as follows. Counter 2 and register 3 are set to the initial state. The initial state of the trigger 5 is assumed to be zero. After feeding the input 14 of the signal device, the Start is on the first, second, third and fourth outputs of the generator 1 and forms signals, respectively, 15 to 18 (FIG. 2), which synchronize the operation of the remaining units of the device. The signal 15, which arrives at the first input of register 3, causes a cyclic shift of register 3 by one bit (the direction of the shift does not matter in principle, but must remain unchanged during the entire operation of the device). Signal 16 arriving at the first input of comparison circuit 4, compares the states of counter 2 and register 3, respectively, entering the first and second inputs of comparison circuit 4. The shift of register 3 and the comparison of the state of the scientific research institute of counter 2 and register 3 takes place until one of the signals 19 or 20, respectively, appears at the first or second outputs of the comparison circuit 4. The occurrence of signal 19, which indicates that the contents of counter 2 is larger than the contents of register 3, entails the appearance of signal 21 at the output of the element OR 11 entering the second inputs of the second and third elements AND 7 and 8. After At the first inputs of the second and third elements AND 7 and 8, respectively, of signals 18 and 17 at the outputs of these elements AND, signals 22 and 23 appear, respectively. The signal 22, arriving at the first input of counter 2, increments counter 2 by one, and the signal 23, arriving at the second input of register 3, records the register 3 that arrives at its third input, the contents of counter 2. The process of shifting register 3, comparing the state The counter 2 and the register 3 in the circuit 4 are comparable to 9 and, when the signal-19 appears, the increase of the counter 2 and the recording of its changed state in the register 3 continues until the second output of the signal-comparison circuit 4 appears. 20 indicates that the contents of the counter 2 are equal to the contents of register 3, and therefore the state of the bits of the register 3 must be connected to the test sequence formed on cumulative register 12. By the signal 20, the trigger 5 is set to the single state, and the output 24 appears at its single output on the second entrances are fourth. of this and the fifth elements And 9 and 10. After entering the first entrances of the Fourth and fifth elements And 9 and. 10, respectively, signals 15 and 16 at the outputs of these elements, AND signals 25 and 26, respectively, appear. Signal 25 arriving at the shift input of cumulative register 12 shifts cumulative register 12 by one bit, and signal 26 arrives at the recording resolution input of cumulative register 12, records the position of the extreme right bit of cumulative register 12 (in the case of register 3 shifts to the left) or to the left (when shifting to the right), register 3 is fed to the first input of accumulative register 12. The storage register 12 is shifted and written to it in parallel to the shift the register 3 and the comparison of the states of the counter 2 and the register 3 in the comparison circuit 4 until those nopj until the first output of the circuit 4 again fails to receive the signal 20, which causes the reset of the tfiger 5 and its appearance on the second ( inverse) the output of the signal that arrives at the second input of the AND 6 element and entails the appearance at the outputs of the AND 6 element, the OR 11 element, the AND 7 and 8 elements, respectively, of the signals 27, 21, 22 and 23, leading to a change in the content counter 2 and the 3Test sequence register becomes ready for use after making f entries in cumulative register 12, where t -, the number of bits. A test sequence that is cyclic.

formed completely after making entries in cumulative register 12.;

As a result of the operation of the device, with n 6 and the initial state of counter 2 and register 3 equal to 001011, the following test sequence is generated: OOfOHOOIIOIOOII11010101010110111111 00000010000110001О1000111001, containing all 64 possible combinations of zeros and ones in six bits.

The proposed device in comparison with the known one has the following advantages: the amount of equipment directly involved in the generation of test sequences is calculated using the formula Sn, which allows using the device for large n, thus providing wide functionality applied to various types of devices and high completeness testing. Compared with devices for generating pseudo-random binary sequences, the proposed device allows, according to a single rule for any n, to generate test sequences containing all possible combinations of zeros and ones in n bits.

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Claims (1)

DEVICE FOR GENERATION OF TEST SEQUENCES, containing a clock pulse generator, a storage register, a trigger and a first element,, the input of the clock pulse generator being the device start input, the accumulating register output as the device output, characterized in that, in order to expand the scope of application of the device the shift register, the comparison circuit, the counter, the OR element, the second, third, fourth and fifth AND elements are introduced, and the first output of the clock generator is connected to the control input a comparison circuit, the first and second information inputs of which are connected respectively to the counter output and the first output of the shift register, the second output of which is connected to the information input of the accumulation register, the shift input and the recording permission input of which are connected respectively with the outputs of the fourth and fifth elements AND, the first inputs of the fourth and the fifth elements of And are connected respectively to the second and first outputs of the clock generator, the second inputs of the fourth and fifth elements of And are connected to the unit output a Igger whose zero output is connected to the first input of the first AND element, the second input of which is connected to a single input of the trigger and the comparison output of the comparison circuit, the non-comparison output of which is connected to the first input of the OR element, the second input of which is connected to the output of the first AND element, the output of the OR element connected to the first input of the third element And, the second input of which is connected to the third output of the clock generator. The output of the third element And is connected to the write enable input of the shift register, the shift input of which is connected with the second output of the clock generator, the reset inputs of the shift register and counter are the input of the initial installation of the device, the information input of the shift register is connected to the output of the counter, the counting input of which is connected to the output of the second element And, the first and second inputs of which are connected respectively to the fourth output of the generator clock pulses and the first input of the third element I. 00 m from 1 _ 1,138,799 2