SU1735846A1 - Pseudorandom pulse sequence generator - Google Patents

Abstract

The invention relates to computing and can be used in systems of automatic monitoring and control in instrumentation. The purpose of the invention is to increase the speed and noise immunity of a pseudo-random sequence generator. The generator contains three registers, four groups of repeaters with three states at the outputs, a control unit, two majority elements, three modulo-two adders, an initial code master, a reversible counter, and a BAN element. The purpose of the invention is achieved by the appropriate connection of the listed blocks, providing a consistent monitoring of the state of the registers and their correction in case of occurrence of failures, as well as the elimination of errors in the organization of feedbacks in the shift registers, 2 Il, 2 tabLa SP

Description

The invention relates to computing and can be used in radio systems, in automatic control and management systems, and in instrumentation equipment.

The purpose of the invention is to increase the speed and noise immunity of a pseudo-random sequence generator.

FIG. shows the block diagram of the generator; 2 is a control block diagram.

The generator contains 1–3 shift registers, the first, second 5, third 6 repeater groups with three output states, control block 7, first major element 8, first 9, second 10, and third 11 modulators two, second second element 12, initial code setpoint 13, reversible counter 1A, fourth group of 15 repeaters with three states at the outputs, clock input 16 of the generator, input 17 of the initial installation of the generator, element BANE 18, output 19 of the generator.

The control unit 7 contains the elements OR NOT 20-22, the comparison circuits 23-25, the permanent memory element 26, the first 27, the second 28, the third 29 and the fourth 30 OR elements, the triggers 31-3, the first 35, the second 36, the third 37 and fourth 38 delay elements, the fifth element OR 39, the element AND kna

The initial code setter 13 consists of two groups of switches: the first one is for Forming

00 01

oo

four

about

the binary code combination corresponding to the number N 2h-1, and the second to form the code of the initial state of shift registers 1-3. The number of switches in the groups is determined by the number of bits of the shift registers used,

The kth and nth bit outputs of each of shift registers 1–3 are connected to the inputs of the corresponding adders 9–11 modulo two, with the number k chosen from the condition of obtaining a pseudo-random sequence of maximum length.

Table 1 shows the corresponding k for a number p and n.

The generator works as follows,

Before starting, the initial code setter 13 generates the code of the initial state of shift registers 1-3, as well as the binary code combination corresponding to the number N 2 - 1 (where N is the number of cycles of a pseudo-random sequence of maximum length; n is the number of bits of each of the registers 1 -3 shift). Then, from the input 17 of the initial installation of the generator to the second single input of the control unit 7, a signal of the initial installation is sent; high impedance state at the outputs of the fourth group of 15 repeaters. The logical O signals that appear on the fifth, sixth, and seventh outputs of block 7 (the initial state is logical 1 levels) set the first 4, second 5, and third 6 groups of repeaters to high, respectively.

five

impedance at their outputs. Thus, on the common information bus, only the initial state code of the registers 1-3 shift from the output of the fourth group of 15 repeaters,

After the delay time t31 (t3i is determined by the speed of the repeater groups), signals 1 appear in the first, second and third outputs of block 7, ensuring that the initial state code is written to all shift registers 1–3. From this point on, the generator is ready to form a pseudo-random sequence „

The clock pulses entering the generator input 16 are fed to the reverse counting input (-1)

0 of the binary counter 14 operating in the subtraction mode from the number to P, and also fed to the clock inputs of the shift registers 1-3, which ensures the change in the state of the bits of these registers. In addition, the clock pulses arrive at the first single input of the control unit 7. The inputs of the second major element 12, which is necessary to eliminate the error in organizing feedback, from the outputs of the first 9, second 10 and third 11 modulo-two adders receive signals representing the sum modulo two k-x and n-th bits of the corresponding

5 registers 1-3 shift. At the output of the majority element 12, a feedback signal is generated that arrives at the serial information inputs of shift registers 1–3, generating a pseudo-random sequence of maximum length M 2n-1 "

A pseudo-random sequence of pulses is removed from exit 19 of the

5 of the rator, which is the output of element 18, is open due to the action at its input of a signal from the eighth output of block 7 and connected by another input to the output of the majority element

0 8 implementing a logical operation

0

0

x

and

X

,, x; 2

1g

);

x;)

i%

x;

x-tV (; x; t

where x;, x, -g

and xi2 (- signals arriving

with i-x bits of the first 1, second 2 and third

th 3 shift registers respectively.

The first major element 8 is necessary to eliminate errors when reading elements of a pseudo-random sequence.

With the arrival of the countdown input (-1) of the reversing counter AND of the last () -th clock pulse for a given pseudo-random sequence of maximum length at the output of the reverse transfer (0 of this counter, a signal arrives at the third single input of the control unit 7 and records the numbers N - 2n-1 into the counter, as well as the entry of the initial state code into all shift registers 1–3, similarly to that indicated for setting the generator to its initial state c,

When generating a pseudo-random sequence of pulses, the contents of shift registers 1–3 at any time before the next clock pulse must arrive at their clock inputs must coincide. The contents of registers 1-3 are analyzed in block 7. In case the registers 1-3 contain the same information, other than zero, then on the first, second, third, fourth, and eighth outputs of the control unit there are logical O signals, and other outputs - logical 1 ,,

If, due to interference, the contents of registers 1 became different from the contents of registers 2 and 3, then at the fifth output of block 7 a logical O signal appears, setting a group of repeaters k to a high impedance state at the outputs. On the common information bus, the same status code of registers 2 and 3 occurs, which is written to register 1 by logical 1 from the first output of block 7, which occurs after the delay time t31. At the eighth output of block 7, there is a logical 1 signal for blocking the generator output 19 during the correction time. The initial state at the outputs of block 7 is established through the delay time t 2 necessary to effect the correction.

When the contents in register 2 differ from the contents of registers 1 and 3, the logical O signal is set

five

0

five

0

A group of 5 repeaters in a high impedance state at the outputs appears at the sixth output of block 7, and a logical 1 signal from the SECOND output of block 7. appearing through the delay time t91, it writes to the shift register 2 the status register of registers 1 and 3, taking place Q on the common information bus.

Similarly, when the signal in register 3 is distorted by a signal from the seventh output of block 7, a group of 6 repeaters is set to high impedance and recording from the common bus the contents of registers 1 and 2 to shift register 3 on the signal from the third output of block 7

When zeroing any shift register 1-3 on the corresponding fifth volume of the sixth or seventh output of block 7, a logical O signal appears, setting the corresponding group A-6 of the repeaters to a high impedance state, and after a delay time t3 from the corresponding first, The second or third output of block 7 appears as a logical 1 signal, recording information from the non-zero (healthy) shift register into a zero register.

If, due to interference, simultaneous zeroing occurred in all three registers 1-3, the shift or the state of each register became different from the state of the other two, then the first, second, third, fourth and eighth outputs of control unit 7 appear in logical 1, and on the remaining outputs - a logical O. There is an entry in the counter Ik of the number N 2л-1 and an entry in the registers 1-3 of the shift of the initial state code, similar to the case of the initial installation of the generator. Exactly the same operations take place at the moment of the end of the period of the generated pseudo-random sequence.

The indicated correction modes of these or other failures are provided by the control unit 7, which operates as follows.

In the initial state, the 31AA triggers are in the zero state. If, due to the influence of interference, any shift register 1-3 is reset, then signals of logical 1 which appear from the outputs of the corresponding elements of OR-NOT 20-22 group,

0

five

0

S

five

pass through the first inputs of the elements OR 27-29, enter the installation inputs in the unit state of the corresponding triggers 32-3 and change their state. As a result, the logical outputs of the inverted outputs of the flip-flops 32-3 appear at the corresponding fifth, sixth, seventh outputs of block 7. The signals of logical 1 from the direct outputs of the flip-flops come through the corresponding identical delay elements 36-38 the first, second, third outputs of block 7, as well as to the corresponding inputs of the fifth element OR 39 and the element AND CO, When the state of at least one of the triggers 32-3 changes, the output of the element OR 39 is a signal of logical 1, which act on the eighth exit block 7, about Provides for blocking the generator output 19 for the duration of the correction.

Elements 36-38 of the group delay are necessary to ensure that the correction information is installed on the common bus before writing it to the corresponding shift registers 1-3 during the correction process. The clock pulses, arriving at the first single input of the control unit 7, passing through the delay element 35 to the installation inputs to the zero state of the triggers 31-34, reset them to the initial state. The delay time t 2 of element 35 must satisfy the inequality

0

S

0

five

logical 1, coming through the first input element OR 27 to the input of the installation in a single state of the trigger 32.

If the information in the shift register 2 is distorted, the code combination 1.0.1 is set at the inputs A, Ar, AЈ of element 26, thereby providing a logical 1 signal at the second output of the element 26 translating the trigger 33 into a single state.

The combination 0,1,1 at the inputs, A, Az of the element 26, which occurs in the case of distortion of information in the register 3, determines the appearance of the signal logical 1 from the third output of the element 26, which, passing through the first input of the corresponding element OR 29, translates trigger 34 in one state.

A combination 1,1,1 from the outputs of the comparison circuits 23-25 takes place if, due to the interference effect, the state of each register becomes different from the other two. In this case, the signals of logical 1 appear on all outputs of the element 26, switching 0 flip-flops 32-34 to one state. Appearance at the inputs of elements of 26 combinations 1,0,0; 0.1.0 and 0.0.1 is excluded by the logic of the device.

Table 2 shows the programming table for setting element 26 of the constant unit (mi.

-ti

Where

The time it takes to make a correction is determined by the speed of the elements; Tti is the period of clock pulses at the input 16 of the generator.

If shift registers 1–3 contain the same information (generator operation is normal), the code combination 0.0.0 enters the address inputs A, Ae, A3 of the element 26 of the post-drop memory from the outputs v of the comparison circuits 23–25; at the outputs of the element 26, there is a zero connection.

i

If, due to the effect of interference, the information in the register 1 was corrupted, then the input combination 1,1,0 is inputted at the inputs A, A / j, A of element 26 from the outputs of the corresponding comparison circuits 23-25. As a result, a signal appears at the first output of the permanent memory element 26.

The logical 1H signal from the output of the first element OR 30 arrives at the installation input to the unit state of the trigger 31 and simultaneously through the third inputs of the OR elements

groups on the same inputs of the flip-flops 32-Z1 are installed in a single state. The signal at the output of the first element OR 30 appears when logical signals 1 from the second or third inputs of block 7 arrive at its corresponding inputs, as well as from the output of the AND element when all of the triggers are in the unit state

Claims (1)

Invention Formula A pseudo-random pulse train containing the first major element, the BAN element, the first, second and third shift registers, the outputs (i 1, n; n is the number of shift register bits) whose bits are connected to the inputs of the first majority element, the output of which is connected to the direct input of the BANCH element, the output of which is the generator output, which is characterized by the fact that, in order to improve the speed and noise immunity of the generator, the first, second third and fourth groups of surfaces are additionally introduced into it viewers with three states at the outputs, initial code adjuster, reversible counter, first, second and third modulo-two adders, second major element and control unit containing three OR-NOT elements, three comparison circuits, permanent memory element, four delay elements, five OR elements, four triggers and an AND element, the bit outputs of the first shift register are connected to the inputs of the first OR element and the first groups of inputs of the first and second comparison circuits, the bit outputs of the second shift register are connected with the inputs of the second element OR-NOT, the second group of inputs of the first and the first group of inputs of the third comparison circuit, the bit outputs of the third shift register are connected to the inputs of the third element OR-NOT and the second groups of inputs of the second and third comparison circuit, outputs Equal to the first, second and second the third comparison circuits are connected to the address inputs of the constant memory element, the first, second and third bit outputs of which are connected respectively to the first inputs 358I10  the first, second and third elements OR, the second inputs of which are connected respectively to the outputs of the lane. the second, second and third elements OR NOT, and the third inputs of the first, second and third elements OR are connected to the output of the fourth element OR ten t5 20 25 thirty 35 40 45 SO 55 and with the installation input in 1P of the first trigger, the outputs of the first, second and third OR elements are connected to the installation inputs in 1 of the second, third and fourth triggers, respectively, the installation inputs in О which are connected to the output of the first delay element and the installation input in O of the first trigger , the direct output of the second trigger is connected to the input of the second delay element, the first input of the fifth OR element and the first input of the AND element, the direct output of the third trigger is connected to the input of the third delay element, the second input of the fifth element and OR and the second input element AND, the direct output of the fourth trigger is connected to the input of the fourth delay element, the third input of the fifth OR element and the third input of the AND element, the output of which is connected to the first input of the fourth OR element, the outputs of the second, third and fourth elements delays are connected to the write control inputs of the first, second, and third shift registers, respectively; the inverse outputs of the second, third, and fourth flip-flops are connected to the control inputs of the repeaters with three states at the outputs correspondingly, the first, second and third groups, the direct output of the first trigger is connected to the control inputs of the repeaters with three states at the outputs of the fourth group and to the enable input of the parallel loading of the reversing counter, the 1st discharge outputs (, n) of the repeaters with three the states at the outputs of all four groups are connected via mounting OR to the i-th information inputs of the first, second and third shift registers; the 1st discharge outputs of the first, second and third shift registers are connected to information inputs n vtoriteley to tri-state the outputs respectively of the first, second, third groups, k-e The discharge outlets (k 2, n-1) first, second and third registers are connected to first vho11 The first, second, and third modulators are, respectively, two, the second inputs of which are connected to the n-th bit outputs of the first, second, and third registers, and the outputs to the first, second, and third inputs of the second major element, the output of which is connected to serial information the inputs of the first, second and third registers, the reverse count input of the reversible counter is connected to the clock inputs of the first, second and third shift registers with the input of the first delay element and is clock2A; 7358I12 the primary input of the generator, the initial installation input of which is connected to the second input of the fourth OR element, the third input of which is connected to the reverse transfer output of the reversible counter, the information inputs of which are connected to the first set of master outputs of the initial 10 code, the second group of outputs are connected to the repeater inputs with three states at the outputs of the fourth group, the output of the fifth element OR is connected to the inverse input J5 of the BAN element.