SU1755286A2 - Device for interfacing computer with peripherals - Google Patents

Abstract

The invention relates to computing, can be used in interface devices of external equipment with a computer channel and for providing autonomous diagnostics of serial storage devices. The aim of the invention is to reduce the amount of equipment and enhance the functionality. For this purpose, a signature generator, a local control unit, two switches, a comparison unit, an initial condition setting unit, a display unit and a key block are entered into the device. 1 z.p, f-ly, 11 ill.

Description

The invention relates to computing, can be used in interface devices of external equipment with a computer channel and for providing offline diagnostics of serial storage devices.

The purpose of the invention is to reduce the equipment volume and extend the functionality by providing autonomous diagnostics of external devices.

FIG. 1 shows a block diagram of the device; in fig. 2 - functional scheme of the second block rewriting; in fig. 3 - the functional scheme of the first rewriting unit; Fig. 4 is a functional block diagram of the control unit; in fig. 5 is a diagram of a readiness block; in fig. 6 is a block diagram of a local control unit; in fig. 7 is a diagram of the signature generator; Fig, 8 is a diagram of the second switch; in fig. 9 and 10 - time diagrams of the recording mode of the device; in fig. 11 is a timing diagram of the reading mode of the device.

The device (Fig. 1) contains the register-receiver 1, the first trigger 2, the register-transmitter 3, the third trigger 4, the second block 5 rewriting information, an external device (WU) 6, the buffer register 7, the second trigger 8, the first block 9 rewriting information, control signal register 10, form-ready readiness unit 11, control block 12, input group 13, local control block 14, signature generator 15, first switch 16, second switch 17, comparison block 18, output groups 19 and 20, block 21 indications, the initial conditions setting unit 22, the first installation input 23 d, the fourth input of the installation 24,

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key block 25, the second installation input 26, the third installation input 27.

The second block 5 rewriting information (Fig, 2) contains the elements OR 28, 29, 30, the elements 31, 32 delays, one-shot 33.

The first block 9 of rewriting information (Fig. 3) contains the elements OR 34, 35, the elements 36, 37, 38, delays, the one-shot 39.

The control unit 12 (FIG. 4) contains elements OR 40, 41, 42, 43 and 44, element AND 45, element AND-NE 46, elements AND 47, 48, 49, 50, 51, 52, 53 and 54, the elements 55, 56, 57, 58 and 59 delays, the counter 60.

Block 11 forming readiness (Fig. 5) contains the elements And 61, 62 and 63, the element OR 64, triggers 65 and 66.

The local control unit 14 (Fig. 6) contains AND elements 67, 68, 69, 70, 71, 72, 73,74 and 75, delay elements 76,77,78,79, trigger 80 and 81 81, element OR 82, counters 83, 84 and 85, the decoder 86, the element is NOT 87.

Signature generator 15 (Fig, 7) contains the elements OR 88 and 89, the adder 90 modulo two, the shift register 19, the decoder 92.

The second switch 17 (Fig. 8) contains elements And 93,94, the element IL AND 95, the element NOT 96,

FIG. 9-11 are indicated pulses: 97 - at the input 27 (Fig. 1, 6), the write pulse; 9S - to the parallel output of the register-receiver 1 (Fig. 1), the presence or absence of information; 99 - at the single output of the trigger 2 (Fig. 1); 100 - at the parallel output of the buffer register 7 (Fig. 1), the presence or absence of information; 101 - single output trigger 8 (Fig, 1); 102 - at the parallel output of the register-transmitter 3 (Fig. 1), the presence or absence of information; 103 - at the single output of the trigger 4 (FIG. 1); 104 — tracking pulses (ICs) (Fig. 4, 6); 105 - at the first control input of the register-transmitter 3, shifting pulses; 106 - at the serial output of the register-transmitter 3 (Fig. 1); 107 - at the output of the counter 60, an overflow pulse; 108 - at the fault input of the register-transmitter 3; 109 - at the zero input of the trigger 4 (Fig. 1); 110 - at the unit output of the flip-flops 81 (Fig. 6); 111 at the output of the decoder 86 (Fig. 6); 112 - at the output of the element And 71 (Fig. 6), control of the mode of operation of the register 91 shift (Fig. 7); 113 - at the output of the element And 74 (Fig. 6), the write pulse and the shift register 91 (Fig. 7); 114 - at the output of the delay element 78 (FIG. 6), a pulse arriving at the input TH of a group of inputs 13; 115 - single output trigger 80

(Fig. 6), the prohibiting impulse, and, in addition, the delay times and the numbers of the delay elements (for example, T 57) are indicated,

The device operates in two modes; at

diagnostic mode and mate mode.

Diagnostic mode. Initially, the groups of information inputs of the register-receiver 1 and the register 10 of control signals are disconnected from the computer and connected to the block specifying the ground conditions, the group of inputs 13 is also disconnected from the computer, and using the key block 25 switches to the third group

the outputs of block 14, the group of information outputs of the registrar 3 is disconnected from the computer and connected to the display unit 21. Next, the device is reset with the signal Reset, which enters the input 26 of the local control unit 14 (Fig. 1 and 6), sets the trigger 80 to the zero state and resets the counters 83.84, 85, then the corresponding output of the third group the outputs of block 14,

through the key block 25 enters the fault input of a group of inputs 13 of the control unit 12 (FIGS. 1, 4), zeroes the counter 60, passes through the OR 44 element and the delay element 58, resets the transmitter-register 3 and, having passed through the delay element 59, arrives at the zero input of the third trigger 4 and resets it to zero. From the first output of block 12, the signal also arrives at the installation input of the second rewriting block 5 (Fig. 2), passes through the OR element 28 and resets the trigger 8, passes through the OR element 29 and zeroed the buffer reparacfp 7, then it goes to the installation the input of the first block 9 overwriting (Fig. 3),

passes through the OR elements 34 and 35 and resets the first trigger 2 and the receiver register 1, respectively. Then the Reset signal goes to the installation input of block 11 (FIG. 5) and resets the triggers 65 and

66. The switches of the unit 22 are set to off.

In the initial state, on all incoming buses there are no enabling signals, the state of the register 10 control

no signal value.

A data array is a certain number of data blocks represented as a continuous binary sequence of bits following with a certain frequency. Each data block consists, in this case, of 10 words, and each word consists of 16 bits. Before the data array is followed by a service word, two of which are determined by the mode of operation (write or read). The remaining bits

used to determine the starting and ending addresses of the data set and other service information.

To implement the write mode, the switch of block 22 (FIG. 13), corresponding to a single bit, is set to the on state and by applying a pulse signal to the control input of the register 10 (Fig. 1) write 1 to the corresponding register bit 10, From the output of this bit Yes, the resolving potential arrives at the second input of the And 45 element (Fig. 4} and the first input of the And 75 element (Fig. 6).

Next, an input potential of high level is supplied to the input 23, which is fed to the first inputs of the And elements 72, 73 of the block 14 (Fig. 6). At the same time, the absence of a high-level permitting potential at the first input of the And 68 element creates a condition in which low level potentials are present at the first input of the And 70 element, at the input of the HE element 87 and the second input of the And 73 element. The low-level potential from the output of the element 73 is fed to the control input of the first switch 16, where we allow the passage of signals from the first group of information inputs to the group of outputs, and the control input of the second switch 17 (Fig. 8), to the input of the element HE 96 and second input element And 94. Arrival at the second input element And 94, it prohibits the passage of signals from the serial information output of the signature generator 15, arriving at the first input element And 94, The potential of a high level from the output element HE 96, and the second input element And 93, allows the passage of signals from the serial information output of the register-transmitter 3, arriving at the first input of the element And 93, through the element OR 95 at the output of the second switch 17.

The low level potential at the input of the HE element 87 of block 14 (Fig. 6) creates at its output a high level potential, which is fed to the second input of the And 75 element, at the first input of which a high potential is already located. The high potential from the output of the element OR 82 and further from the corresponding output of the fourth group of outputs of block 14 is fed to the input of the group of control inputs of the signature generator 15 (Fig. 7) and adjusts the shift register 91 to the recording mode.

Next, a control signal 24 is supplied with a pulse signal, which passes through the element OR 88 (Fig. 7) and, at the input to the pre-entry strobe

the shift register 91, records the key word defining the content of the data array, the code of which is supplied from the first group of outputs of block 22 (Fig. 1) to

the first group of information inputs of the first switch 16, and from its output enters the group of information inputs of the signature generator 15,

Lack of resolving potentials

0 at the first inputs of the elements And 52 and 45 (Fig 4) and at the inputs of the element And 48 creates conditions under which the corresponding potentials from the output of the element And 48 and the element OR 43, entering the inputs of registers 1 and 3,

5 set them up to record mode. Then a service word is recorded, the code of which is fed to the parallel input of the register-receiver 1 from the second group of outputs of block 22. Record impulse (97, Fig. 9)

0 is fed to the input 27, then through the key block 25 enters the corresponding bus of the group of inputs 13 of the control unit 12, passes through the OR 40 element and, arriving at the control input of the register-receiver 1,

5 records the service word (98, fig. 9)

The write pulse from the output of the IL element 41 is delayed by the element 57 for the duration of the transient processes in register 1 and arrives at the single input of trigger 2, setting it to the single state (99, Fig. 9). Allowing potentials from a single output of the trigger 2 and the zero voltage trigger 8 trigger one5 vibrator 39 (Fig. 3). The impulse from the output of the single vibrator 39 is delayed by the element 38 for the duration of the transient processes in register 7 and, arriving at its input, records the service word from register 1 (100, Fig. 9).

Then this pulse is delayed by element 37 for the duration of the pulse, passes through the element OR 34, resets trigger 2 to the zero state, after which

5 is delayed by element 36 for the time it takes to set trigger 2 to the zero state and sets trigger 8 to one state (101, Fig. 9), then, passing through the OR element 35, resets the receiver register

0 1 (98, fig. 9).

Allowing potentials from a single output of the trigger 8 and zero output of the trigger 4 (Fig. 1) trigger the one-shot 33 of the second block 5 rewriting information

5 (FIG. 2). The pulse from its output passes through the element OR 30 and records the service word in the register-transmitter 3 (102, Fig. 9). Then the pulse is delayed by element 32 for the duration of the pulse, passes through the element OR 28 and the trigger 8 is triggered to the zero state. After that, the pulse is delayed by element 31 on the transitional process termination burden when throwing trigger 8, sets trigger 4 to one (103, Fig. 9) and, passing through the OR element 29, resets the buffer register 7 to zero.

So, the service word recorded in the register-receiver 1, rewritten in the register-transmitter 3.

The zero state of trigger 2 allows further writing to the receive register.

1. The zero information is written to the receiver register 1. Likewise, the zero information is rewritten and the free buffer register 7 is written. At the same time, the trigger 8 is set to one. The secondary recording of zero information in the register-receiver 1 sets the trigger 2 to one state.

The presence of low-level potentials at the third input of the element And 69 (Fig. 6), the first input of the element And 71 and the second passage of the element And 72 prohibits the passage of several signals in the recording mode,

Simultaneous Detection of Triggers

2.4 and 8 in the unit state and the number of units in the register register 10 defining the recording mode (GTP) is a necessary and sufficient condition for generating a signal. The beginning of the BUT exchange determines the beginning of the transfer mode of the pseudo-random sequence generated by the signature generator. 15, i.e. the resolving potential from the output of the element AND 61 (Fig. 5) passes through the element OR 64 and outputs the trigger 66 to one state. The resolving potentials from the zero output of the trigger 65 and the single output of the trigger 66 arrive at the inputs of the element I 63, from whose output the signal BUT is fed to the control input of the VU 6 (the beginning of the generation of the signal BUT in Fig. 9 is indicated by a dotted line).

In response to the BUT signal, the external device generates a series of ICs (tracking pulses) the number of which is equal to the number of bits of the register-receiver 1. The first IC goes to the single input of the trigger 65 of block 11 (Fig. 5) and sets it to the single state. The inhibitory potential from the zero output of the trigger 63 stops the signal BUT in WU.

IS 1049FIG. 10) passing to the first input of the control unit 12, are delayed by element 56 for the duration of the action of the IC, are fed to the second input of the element AND 51, at the first input of which there is a resolving potential from the output of the element 45, pass through the elements AND 51 and OR 42 and arrive at the third launch input of the second information rewriting unit 5 (FIG. 2). After passing through the element OR 30, the pulses 105 (Fig. 10) arrive at the control input of the register-transmitter 3 and shift the right of the service word in it. The overhead word from the serial output of the register-transmitter 3 passes through the elements AND 93 and OR 95 (Fig. 8) and in the serial format (106, Fig, 10) we are input to the WU 6. The last IC causes overflow of the counter 60 of the control unit (107, Fig. 10) passes through the elements of AND 54 and OR 44, is delayed by the element 58, resets the register 3 (108, Fig. 10), is delayed by the element 59 and resets the trigger 4 (109, Fig. 10).

When transmitting the SS, the tracking pulses also pass through the element And 67 of the block 14 (Fig. 6), since, at the second input, there is a resolving potential, are delayed by the element 76 and arrive at

counting input counter 83.

The capacity of the counter 83 is equal to the size of the registers 1, 7, 3. Therefore, when transmitting the CC, the last IC of the accompaniment zeroes the counter and the counter overflow pulse

but passes through element 70, since at its first entrance there is a forbidding potential.

The ICs from the output of the delay element 76 arrive at the synchronous input of the shift register 91 (FIG. 7), but since it is set to the recording mode, the information in the register does not shift.

The service word recorded in the VU is analyzed, after which the Ready G signal will be output from the VU indicating that it is ready to receive the data sequence. A high potential signal G is fed to the first input of the element.

And 68 of the local control unit 14 (Fig. 6), at the second input of which there is a high level potential from the single output of the trigger 80. Therefore, from the output of the And 68 element, the potential of the high level

arrives at the second input of the element And 73, at the first input of which a high level potential is already present. The high potential from the output element And 73, arriving at the control input of the second switch 17

(Fig. 1, 8) prohibits the transfer of information from the output of the register-transmitter 3 and allows the transfer of information from the serial output of the signature generator 15 to the input of the low voltage switchboard. Therefore, further changes in the state of the element of blocks 12, 9, 5 of registers 1, 7, 3, triggers 2, 8, 4, when operating in the described mode, do not matter.

The resolving potential of the high level from the output of the element And 68 enters the input of the element HE 87. Therefore, the potential of the low level from the output of the element NOT 87 goes to the second input of the element AND 75, passes the element OR 82, from the output of which the potential of the low level goes to the input of the generator 91 shift (Fig. 7) and adjusts it to the shift mode.

The tracking pulses, outputted by WU 6 when recording the data array, pass through AND 67 (Fig. 6), are delayed by element 76 for the duration of the pulse, arrive at the synchronous input of the register 91 of the shift signature generator 15 (Fmg. 7) and shift to the right information in it. In this case, the logical values of the feedback bits of the register 91 are summed modulo two with the logical values fed to the single input of the adder 90 and from the output of the adder 90 are fed to the serial input of the shift register 91 and the second input of the second switch 17, pass through the AND elements 94 and OR 95 and from the output of the second switch 17 are fed to the information input of WU 6. At the same time, if the bits of the register 91 are in the state 11 ... 10 or 11 ... 11, the outputs of which are connected to the decoder 92, then low level inhibitory potential A logical zero, from the output of the OR-NOT 89 element, arrives at the single input of the adder 90. Thus, the logical zero signal arriving at the single input of the adder 90 results in modulo two with the logical signals arriving at its input group with code 11. .. 10, gives the output of the adder 1, and with the code 11 ... 11 - for all other values of the codes of the register 91 from the output of the adder 90 enters 1,

The overflow pulses of the counter 83, corresponding to the end of the recording of the data word, pass through the element 70 and are delayed by the element 77 for the duration of the transient processes in the counter 83, arrive at the counting input of the counter 84, which counts the number of words. The overflow pulses of this counter, corresponding to the end of the recording of a block of data, arrive at the counting input of counter 85, which counts the number of recorded blocks of data.

The number of ICs coming from WU 6 must be equal to the number of bits of the transmitted data array.

After transmitting the data array, the Ready signal is removed. Number recorded

data blocks recorded in the counter 85 (Fig. 6). Then the code of the block number from the group of outputs 19 is supplied to the third group of inputs of the display unit 21.

To implement the read mode, the device is reset. Then the switch of the block 22 corresponding to the zero-bit is set to the on state, just what the high-level permitting potential is applied to the input 23. A unit is then written to the corresponding register bit 10.

The resolving potential from the output of the raz5 p yes register 10, which determines the reading mode, goes to the inputs of the elements 47, 48, 49 (Fig. 4), to the other inputs of which goes to the inhibitory potential from the bus T, and to the second input of the element 52. ,

0 to the third input of which the resolving potential comes from the output of element I 46, and the first input is connected to the single output of the trigger 4, which determines the setting of the register-transmitter 3 for the mode

5 records. The absence of the resolving potential at the first input of the element And 48 creates at the output of this element a potential that adjusts the register-receiver 1 to the mode of recording information in parallel

0 format. Further, similarly to the recording mode, the overhead word is recorded, which appears in the register-transmitter 3, and the trigger 4 is set to one state.

5 A necessary and sufficient condition for generating a BUT signal in the read mode is the presence of a unit in the corresponding register register 10 and finding the trigger 4 in the unit state, Solving potentials from the outputs of these elements are fed to the inputs of the And element 62 (Fig. 5).

The resolving potential from the output of the element AND 62 of the block 11 (FIG. 5) passes the element OR 64 and sets the trigger 66 to one state. The further work of block 11 on the generation of the signal BUT and the transfer of the service word from the register-transmitter 3 to the VU 6 takes place analogously to the mode

0 records.

After receiving the service word, WU 6 sets the Ready signal. The resolving potential arrives at the first input of the AND 48 element (Fig. 4), at the second input of which there is a resolving potential determining the reading mode. From the output of the And 48 element, the resolving potential adjusts the receiver-register 1 to the shift mode. From the output of WU 6, information in a sequential format is fed to a sequential

the input of the register-receiver 1, the IC, the number of which is equal to the number of bits of the transmitted data array, is fed to the input of the delay element 55, the control unit 12, is delayed by the time ensuring the establishment of the signal level at the serial input of the register-receiver 1 corresponding to a certain information bit, and sprinkle on the third meeting of the element And 47, on the remaining inputs of which the resolving potentials are present, From the output of the element 47, the IC passes through the element OR 40 and goes to the control input of the register-receiver 1, recension shift information. In this case, with the bit of each word raised, counter 60 overflows. Pulse 107 {FIG. 1 i) the overflow passes through the terminals of g & 49, the remaining potentials are supplied to the remaining inputs of the golden cup. The OR element 41 is delayed by element 57 on the Transition Burm in receiver-register 1 and sets the first trigger 2 to one (99, Fig. 11). Allowing potentials at the input of the Si oscillator of the information rewriting unit 9 start it. A pulse from the output of the one-shot 39, a pass delay element 38, will write the information word from the register-receiver 1 to the buffer register 7 (100, Fig. 11). Similarly, this information is copied to the register-transmitter 3.

An overflow impulse from the output of counter 83 sets the trigger 81 to the one state, and the next JC resets it to zero. From the single output of the flip-flop 81, pulse 110 (Fig. 11) arrives at the second input of the And 71 element. After receiving the first word of each data block, the overflow pulse passes through the And 70 element, is delayed by the element 77 during the transients, the counter 83 and enters the counting input of the counter 84. At the moment when the counter 83 is zeroed out, and the unit 84 is recorded as the recorded unit, from the output of the decoder 86, the high level potential arrives at the third input of the And 71 element (111, Fig. 11). The potential of the high level from the output of the element And 71 (112, Fig. 11) passes the element OR 82 and adjusts the shift register 91 (FIG. 7) to the recording mode.

The write pulse to the register 3 from the output of the OR element 30 of block 5 (fig. 2) enters the input of element1 79 of block 14 (fig. B), is delayed by the time of transients in register 3, passes through the element 74 and 74 (fig. 14), the element OR 88 (Fig. 7} and records (113, Fig. 11) of the first word

of data in register 3 to shift register 91 (FIG. 7), which passes through switch 16, which is high potential from the output element

And 73 (FIG. 6) is configured to transmit information from the second group of information inputs to the group of information inputs of the signature generator 15 (FIG. 1.7). The information from the outputs of register 3 and the natural field generator 15 is compared by comparison unit 18. If the comparison is made, a low level potential is supplied from the output of block 18 to the second input of element AND 69 of block 14, which prohibits the pulse from passing (114, Fig. 11) from the output of element OR 29 (FIG. 2) through element 69 (Fig b) on the single input of the trigger 80.

The pulse from the output of the delay element 79 (FIG. 5) is delayed by the element 78 on

0 time of action of this pulse, passes through the element AND 72 (114, Fig. 11), on the remaining inputs of which high level potentials are present, and goes to the first descent of the element OR 44

5 (FIG. 4). From the output of the element, the pulse is delayed by element 58 and resets the register 3 (102, Fig. 11), is delayed by element 59, and resets trigger 4 (103, Fig. 11).

0 So, the key word read from WU 6 is written to register 91 of the signatures of the south generator 15. When reading the following words, a similar comparison of the word read from BB 6 to the word occurs, and the input 5 is written in register 91, which is the reference word, so how the change in the contents of this register occurs in the same way as the recording mode.

If the word read from WU 6 is

0 is erroneous, as a result of the incomparability in block 18, to the second input of element And 69 (FIG.

6) a high level potential enters which permits the passage of a pulse arriving at the first input of the element AND

5 69. The trigger 80 sets to one state, and the low level inhibitory potential from the zero output (115, FIG. 11) prohibits the passage of signals through the elements And 67, 68, 72. At the same time, the contents of register 3 are not reset.

So, in register 3 is read

from WU erroneous word in register 91 (FIG,

7) there is a reference word, counter 84 (FIG. 6) contains the sequence number of the word in

5, and the counter 85 (FIG. 5) contains the sequence number of the data block.

Information from the group of outputs 19 and 20 goes to the display unit 21 (FIG. 12), which allows to determine the address of the erroneous word.

The first and fourth groups of inputs of the block 21 from the register-transmitter 3 and the signature generator 15 allow one to determine the error bits of the read word.

Pairing Mode

In this mode, the key block 25 is disabled, the group of information inputs of the register-receiver 1, the inputs of the register 10, the group of inputs 13 and the group of information outputs of the register-transmitter 3 are connected to a computer; a low-level potential is supplied to the inputs 23, 24, 26.27. , blocks 14, 15, 16, 18 are not involved in the operation of the device. In this case, the low level potential from the output of the element And 73 of the block 14 is fed to the control input of the switch 17 and adjusts it to output information from the serial output of the register-transmitter 3 to the input of the VU 6.

The device is reset by the Reset signal, which is fed to one of the three buses of the input group 13 of the control unit 12 (Fig. 1 and 4).

In the recording mode, after writing the service word to the register-receiver 1 and rewriting it in the register-transmitter 3, the zero state of trigger 2 allows further writing of data to the register-receiver 1. The first word of the transmitted data array recorded in the register The receiver 1 is similarly rewritten into a free register 7. In this case, the trigger 8 is set to one.

The second word of the transmitted data array, written in the register-receiver 1, remains in it, and the trigger 2 is set to one.

The simultaneous presence of triggers 2, 4, and 8 in the unit state and the presence of a unit in the register register 10, which determines the recording mode, is a necessary and sufficient condition for the generation of the NO signal. Further, the operation of the device is carried out similarly to the recording mode during diagnosis.

After transmission of the overhead word to WU 6, register-transmitter 3 and trigger 4 are also reset to zero.

The inhibitory potential from a single output of trigger 4 enters the first inputs of elements And 52 and 45, the inhibitory potentials from the outputs of which arrive at the inputs of the element OR 43 and create the corresponding potential at the control input of the register-transmitter 3, switching it to the recording mode.

By setting the trigger 4 to the zero state, the resolving potentials arrive at the inputs of the one-shot 33 (FIG. 2) and start it. Single shot impulse

33, passed through the element OR 30, arrives at the first input of register 3 and records information from the buffer register 7 into it. This same pulse, delayed by element 32, passes through the element OR 28 and resets trigger 8. Then the pulse, delayed by element 31, arrives at the single input of the trigger 4 and sets it to the single state, and, passing through the OR element, resets the buffer register 7 (Fig. 2).

Setting the trigger 8 to the zero state creates the condition for starting the one-shot 39 (Fig. 3). The pulse from the output of the one-shot 39, delayed by the element 38 for a time, ensuring the end of the transition process in the buffer register 7 when it is dropped, goes to its recording input and records information from the register-receiver 1. Then this pulse passes through the delay elements 37 and OR 34 resets the trigger 2 to the zero state and, having passed through the delay element 36, sets the trigger 8 to the one state, and, after passing through the OR element 35, resets the receiver-register 1.

So, after issuing the service word in the slave, the released register-transmitter 3 records the first word of the transmitted data array from buffer register 7, and the second word of the transmitted array located in receiver-register 1 is rewritten into buffer register 7.

Trigger 2, being in the zero state, characterizes the readiness of receiver-register 1 to receive the next word of the transmitted data array,

The service word recorded in WU 6 is analyzed, after which Woo 6 is issued a Ready signal indicating that it is ready to receive an array of data.

Bus G of control unit 12 is connected to the first inputs of elements AND 48 and 49 and through the element IS-NOT 46 to the third input AND 52 and the second input AND 54. In the recording mode, all the listed elements AND are blocked by the inhibitory potential from the output of the register 10 defining the reading mode. Therefore, the inhibitory potential from the output of the element And 48 adjusts the register-receiver 1 to record information from the parallel input, and the register-transmitter 3 adjusts to shift the recording (inhibiting) potential from the single output of the trigger 4, which comes to the first input of the element And 45, at the second input of which the resolving potential is already located, and the passage through the element OR 43 is fed to the control input of the register-transmitter 3. Further

the transfer of the data array in the recording mode is performed in the same way as the transfer of the service word. The number of NS coming to the inputs of the counter 60 and the delay element 56 must be equal to the number of bits of the transmitted data array.

After transmitting the data array, the Ready signal is removed.

The reading mode is implemented in the same way as the reading mode described in the first stage. In this case, the record in the transmitter-register 3 of the service word of the transmitted data array is the unit state of flip-flop 4, which permits reading of the program-accessible register 3. When this register is read, the read pulse arrives on the 4T bus of the group of inputs 13 of the control unit 12, passes through the element OR 44, is delayed by element 58 and resets the register-transmitter 3 to zero, is delayed by element 59 and resets the zero trigger 4.

In this way, the entire array of transmitted data is read, for example. ... the new and final address of which is indicated in the service word.

Claims (2)

1. A device for interfacing a computer with an external device according to cars, N 1397925, characterized in that, in order to reduce the amount of equipment and enhance functionality by providing autonomous diagnostics of external devices, a signature generator, a local control unit, two switch, comparison unit, initial conditions setting unit, key block, the first group of information inputs of the first switch is connected to the first group of outputs of the initial conditions block, information group the inputs of the register of the receiver and the group of information inputs of the register of control signals are connected respectively to the second and third groups of outputs of the initial conditions block, the group of information outputs of the register transmitter is connected to the first group of information inputs of the comparison block, the second group of information inputs of the first switch and the first group of information the inputs of the display unit, the information output of the register of the transmitter is connected to the first information input of the second switch, the output of the cat cerned is the output device for connection to an external data input device, the first and second local group control unit outputs are connected respectively to the second and third groups of information inputs of the indication unit, the first group of the logical conditions, the control unit input is connected via the key block to the third group of outputs of the local control unit, the group of information outputs of the signature generator is connected to the second group of information inputs of the comparison unit and the fourth group of information inputs of the display unit, the first, second and third inputs of the logical condition of the local control unit and the installation inputs of the signature generator and the control register signals are 5, respectively, the first, second, third, fourth, and fifth installation inputs of the device, with the group of inputs of the operation code of the local control unit being connected to the group of information outputs 0 control signal registers, the fourth and fifth inputs of the logic condition of the local control unit are connected respectively to the first and second inputs of the logic condition of the control unit, the sixth and 5, the seventh inputs of the logical condition of the local control unit are connected respectively to the first and second installation outputs of the second rewriting unit, the eighth input of the logical condition of the local control unit is connected to the output of the reference unit, and the output of the local control unit is connected to the control inputs of the second second switch, the second information input the input of the second switchboard is connected to the information output of the signature generator, the group of information inputs of which is connected to the group of information outputs s of the first switch, and the fourth group chet0 Wertz local group control unit outputs coupled to a group signature generator steering inputs. 2. The device pop, 1, differs5 so that the local control block contains nine AND elements, a NOT element, four delay elements, a decoder, an OR element, two triggers and three counters, with the first input of the first AND element 0 is connected to the first input of the second element AND, and is the first installation input of the block, the output of the first delay element connected to the counting input of the first counter, and the output of the epec 5 OR and the output of the third element And form the fourth group of outputs of the block, the zero input of the first trigger connected to the reset inputs of the first, second and third counters and the second installation input of the block, together with the output of the first element And output connected to the third input of the logical condition of the block, form the third group of outputs of the block, the first inputs of the fourth and fifth elements of And are respectively the fourth and fifth input of the logical condition of the block, the first and second inputs of the sixth element And are respectively the sixth and the eighth input of the logical condition of the block, the input of the second delay element is the seventh input of the logical condition of the block, the third input of the sixth element And connected to the first input of the seventh element And and the second input of the first And, together with the first input of the ninth element, they form a group of inputs for the operation code of the block, a group of information outputs of the third counter and a group of information outputs of the second counter connected to the first group of information inputs of the decoder are, respectively, the second and first groups of outputs of the block, output The second element And is the control output of the block, and the output of the sixth element And is connected to a single input of the first trigger, the zero output of which is connected to the third input of the first epec , The second inputs of the fourth and fifth AND gates, an output of the fourth AND connected to the zero input of the second trigger and the input of the first delay element, in addition, the counting input of the third counter is connected to the overflow output of the second counter, the counting input of which is connected to the output of the third delay element, the input of which is connected to the output of the eighth element And, the first input of which is connected to the fourth input of the sixth element And, the output of the fifth element And, the second input of the second element And and the input of the element NOT, the output of connected to the second input of the ninth element AND, the output of which is connected to the first input of the element OR, the second whose input is connected to the output of the seventh element And and the first input of the third element And, the input of which is connected to the output of the second and fourth input of the delay elements, while the output of the fourth delay element is connected to the fourth input of the first element And, the second input of the seventh And element is connected to a single the output of the second trigger, the single input of which is connected to the second input of the eighth element AND and the overflow output of the first counter, the group of information outputs of which is connected to the second group of information data inputs of the decoder, the output of which is connected to the third input the seventh element I. from # -l- 0.7 8 from-29/2 From} Ki KSO i - / g5 FIG 4 0/10 ff / nB About t in A- / J 25 27 Fig7 from 5 97 L 0/77/5 from № 9IG R 93 eleven 95 L  Rig 9. Rig Yu fig // Editor I. Casard Tehred M. Morgenthal Order 2894 Circulation: Subscription VN1 / 1IPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, 4/5 Raushsk Nab. Production and Publishing Combine Patent, Uzhgorod, Gagarin st., 101 Proofreader N.Milyukova