JPH0637351Y2 - Logistic pattern Energy generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a logic pattern generator for supplying test data to a logic circuit to test whether the logic circuit operates normally.

[Prior Art] In the conventional logic pattern generator, the address of the memory that stores the test parallel data is sequentially read by the address counter supplied with the clock pulse, and the read and synchronized test parallel data is loaded into the driver. It was supposed to output via.

By inputting this data to the logic circuit, it is possible to test whether the logic circuit operates normally.

[Problems to be solved by the invention] However, in actual data, since the propagation delay time and the pulse rise time are different for each bit of the parallel data, the timing may be shifted, which may cause the logic circuit to malfunction. is there.

The conventional logic pattern generator has a problem that it is not possible to test the allowable range of such timing deviation.

[Means for Solving Problems] In the logic pattern generator according to the present invention, in order to solve the above problems, a clock pulse generator and a frequency divider for dividing the output of the clock pulse generator into 1 / N. A frequency divider, a counter for counting the output of the frequency divider, storage means for advancing an address with the output of the counter to store parallel data for testing, and the parallel data for testing from a plurality of data output lines of the storage means. Variable delay means provided for each of the plurality of data output lines for inputting, and delay amount varying means for varying the delay amount provided for each variable delay means are provided, and the output of the clock pulse generator is The delay clock signal of the variable delay means is used.

[Operation] Since the output of the storage means for storing the test parallel data is added to the address counter for advancing the address counter, the output of the clock pulse generator is added via the frequency divider for dividing to 1 / N. The pulse output of the clock pulse generator is N while advancing the address of the storage means by one.
Are output individually.

On the other hand, a variable delay means is provided for each of a plurality of data output lines for inputting test parallel data from a plurality of data output lines of the storage means, and the output pulse of the clock pulse generator is directly added as a delayed clock signal. The amount of data delay is increased for each pulse.

At this time, N pulses are added to the delayed clock signal each time the test parallel data advances by one address, and therefore a predetermined delay amount is selected and output for each force line in which N stages of delay amount can be selected for each address.

[Embodiment] A preferred embodiment of the present invention will be described with reference to the drawings.

A logic pattern generator is shown in FIG. 1 so that test parallel data stored in advance are sequentially output. The cycle of the clock pulse output from the clock pulse generator 10 can be switched by the changeover switch 11. This clock pulse is frequency-divided by the frequency divider 12 to generate a count-up signal, which is supplied to the counter 14 via the AND gate 13. The AND gate 13 is opened when the Q output of the RS flip-flop 15 becomes high level (H). The start switch 16 is connected to the set input terminal S of the RS flip-flop 15, and the reset input terminal R of the RS flip-flop 15 and the clear input terminal CL of the counter 14 are connected.
A reset switch 17 is connected to R. When the start switch 16 is turned on, the Q output of the RS flip-flop 15 becomes H, and when the reset switch 17 is turned on, this Q output becomes low level (L) and the counter 14 counts. The value is cleared. The count value of counter 14 is a memory
18 first memory 19 and second memory 20, respectively,
Data stored at sequentially specified addresses is a delay circuit
It is supplied to 21 and 22. The delay circuits 21 and 22 delay the input bit data by a set time and output it. The delay circuits 21 and 22 can set different delay times. The bit data output from the delay circuits 21 and 22 are supplied to the drivers 23 and 24, the signals are amplified, and are supplied to the logic circuit (not shown) to be tested via the output terminals 25 and 26.

A circuit for writing data in the memory 18 is omitted in FIG.

Next, an example of the delay circuit 21 will be described with reference to FIG. The delay circuit 21 includes a shift register 27 and a first memory 19
The bit data from is delayed. The shift register 27 connects the Q output terminals and the D input terminals of the D flip-flops 28 to 31 in cascade, and each clock input terminal CK
Are connected in common. D flip-flop
Bit data from the first memory 19 is supplied to the D input terminal of 28, and a clock pulse from the clock pulse generator 10 is supplied to each clock input terminal CK. Each Q output terminal of the D flip-flops 28 to 31 is a changeover switch.
Connected to 32 terminals a to d, any one of these terminals is connected to the common terminal e and delayed bit data
Supplied to 23.

When the clock pulse period is T and the pulse width is t, the delay time is t when the common terminal e is connected to the terminal a, t + T when the common terminal e is connected to the terminal b, and t + 2T when the common terminal e is connected to the terminal c. , When the common terminal e is connected to the terminal d, t + 3T is obtained.

The delay circuit 22 has the same configuration as the delay circuit 21, and its components will be described using the same numbers as the components of the delay circuit 21.

Next, the operation of this embodiment configured as described above will be described with reference to FIG.

Test data is written in the memory 18 by a write circuit (not shown). Then, the delay times of the delay circuits 21 and 22 are set.
For example, for the delay circuit 21, the changeover switch 32 is switched to connect its common terminal e to the terminal b, and for the delay circuit 22, the common terminal e of the changeover switch 32 is connected to the terminal a. The output terminals 25, 26 are then connected to the input terminals of the logic circuit to be tested. Further, the changeover switch 11 is operated to select the cycle of the clock pulse. Next, when the start switch 16 is turned on, the Q output of the RS flip-flop 15 becomes H, the AND gate 13 is opened, and the count-up signal from the frequency divider 12 passes through the AND gate 13 to the counter.
The original bit data X and Y are supplied from the first memory 19 and the second memory 20 to the delay circuits 21 and 22. FIG. 3 shows an example of the original bit data X, Y. In this case, the delay circuits 21, 22 output the delayed bit data X2, Y1 shown in FIG. 3, and the drivers 23, 24 respectively. Is supplied to the logic circuit to be tested via. In this example, the delayed bit data X2 is the delayed bit data Y1.
The transfer is delayed by one cycle of the clock pulse.

When the stop switch 17 is turned on, the RS flip-flop
The Q output of 15 becomes low level, the AND gate 13 is closed, the count value of the counter 14 is cleared, and the data of the address 0, for example (0, 0), is stored in the memory 18.
Will always be output from.

In this embodiment, a shift register 27 is used as the delay circuits 21 and 22.
Therefore, the ratio of the delay time to the 1-bit transfer time is constant even if the changeover switch 11 is changed to change the cycle of the clock pulse.

The delay circuits 21 and 22 may be configured to use a delay line, which is a distributed constant circuit, instead of using the shift register 27, and change the delay time by switching the connection of the taps. Further, the memory 18 may output parallel data of 3 bits or more. Furthermore, the delay circuit 21 may be connected to at least one of the data output lines DO of the memory 18.

[Effect of the Invention] In the logic pattern generator according to the present invention, the delay means is connected to the data output line of the storage means for storing the test parallel data, and the bit data output from the data output line is delayed by the set time. Since it is possible to output each bit data by shifting for a predetermined time, it is possible to know the allowable range of the timing deviation of each bit of the parallel data supplied to the logic circuit to be tested. Have the effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a logic pattern generator showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of a delay circuit, and FIG. 3 is a waveform diagram used for explaining the operation of the delay circuit shown in FIG. . 14 …… Counter 18 …… Memory 21 …… Delay circuit

Claims (1)

[Scope of utility model registration request] 1. A clock pulse generator, a frequency divider for dividing the output of the clock pulse generator into 1 / N, a counter for counting the output of the frequency divider, and an address by the output of the counter. Storage means for storing the advance parallel data for test; variable delay means provided for each of the plurality of data output lines for inputting the parallel data for test from the plurality of data output lines of the storage means; A logic pattern generator, characterized in that a delay amount varying means for varying the delay amount is provided for each means, and the output of the clock pulse generator is a delayed clock signal of the variable delay means.