JPS635482U - - Google Patents
Info
- Publication number
- JPS635482U JPS635482U JP9838786U JP9838786U JPS635482U JP S635482 U JPS635482 U JP S635482U JP 9838786 U JP9838786 U JP 9838786U JP 9838786 U JP9838786 U JP 9838786U JP S635482 U JPS635482 U JP S635482U
- Authority
- JP
- Japan
- Prior art keywords
- data
- storage means
- output
- bit data
- outputting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案の実施例を示すロジツクパター
ンジエネレータの回路図、第２図は遅延回路の一
例を示す図、第３図は第２図に示す遅延回路の動
作説明に供する波形図である。
１４……カウンタ、１８……メモリ、２１……
遅延回路。
Fig. 1 is a circuit diagram of a logic pattern generator showing an embodiment of the present invention, Fig. 2 is a diagram showing an example of a delay circuit, and Fig. 3 is a waveform diagram for explaining the operation of the delay circuit shown in Fig. 2. It is. 14...Counter, 18...Memory, 21...
delay circuit.
Claims (1)
記憶手段のアドレスを所定の順序で指定して該記
憶手段の複数のデータ出力線から該データを出力
させるアドレス指定手段と、入力端子が該データ
出力線に接続され入力されるビツトデータを設定
時間遅延させて出力する遅延手段と、を有するこ
とを特徴とするロジツクパターンジエネレータ。 storage means for storing test parallel data; addressing means for specifying addresses of the storage means in a predetermined order to output the data from a plurality of data output lines of the storage means; and an input terminal configured to output the data. 1. A logic pattern generator comprising: a delay means connected to a line for delaying input bit data by a set time and outputting the delayed bit data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986098387U JPH0637351Y2 (en) | 1986-06-28 | 1986-06-28 | Logistic pattern Energy generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986098387U JPH0637351Y2 (en) | 1986-06-28 | 1986-06-28 | Logistic pattern Energy generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS635482U true JPS635482U (en) | 1988-01-14 |
| JPH0637351Y2 JPH0637351Y2 (en) | 1994-09-28 |
Family
ID=30966277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986098387U Expired - Lifetime JPH0637351Y2 (en) | 1986-06-28 | 1986-06-28 | Logistic pattern Energy generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0637351Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5954857U (en) * | 1982-10-01 | 1984-04-10 | 株式会社アドバンテスト | delay time control device |
-
1986
- 1986-06-28 JP JP1986098387U patent/JPH0637351Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5954857U (en) * | 1982-10-01 | 1984-04-10 | 株式会社アドバンテスト | delay time control device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0637351Y2 (en) | 1994-09-28 |
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