JPS5986742U - Programmable timing generation circuit - Google Patents

Programmable timing generation circuit

Info

Publication number
JPS5986742U
JPS5986742U JP18145982U JP18145982U JPS5986742U JP S5986742 U JPS5986742 U JP S5986742U JP 18145982 U JP18145982 U JP 18145982U JP 18145982 U JP18145982 U JP 18145982U JP S5986742 U JPS5986742 U JP S5986742U
Authority
JP
Japan
Prior art keywords
generation circuit
timing generation
programmable timing
circuit
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18145982U
Other languages
Japanese (ja)
Inventor
山下 修史
大橋 清一
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP18145982U priority Critical patent/JPS5986742U/en
Publication of JPS5986742U publication Critical patent/JPS5986742U/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の回路構成例を示すブロック図、第2図
は第1図の回路構成例により生成される信号のタイミン
グチャート、第3図は回路構成例のROM内容を示す。 なお図において、1・・曲バイナリカウンタ、2・・・
・・・ROM、3・・・・・・レジスタ、4・・・用イ
ンバータを示す。   ・
FIG. 1 is a block diagram showing an example of the circuit configuration of the present invention, FIG. 2 is a timing chart of signals generated by the example of the circuit configuration of FIG. 1, and FIG. 3 shows the contents of a ROM in the example of the circuit configuration. In the figure, 1... song binary counter, 2...
. . . ROM, 3 . . . register, 4 . . . inverter.・

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 記憶回路と、カウンタ回路とを組み合せ、前記記憶回路
の内容を変えることにより所望の周期のタイミング信号
を発生するようにしたことを特徴とするプログラマブル
タイミング発生回路。
1. A programmable timing generation circuit, comprising a combination of a memory circuit and a counter circuit, and is configured to generate a timing signal of a desired cycle by changing the contents of the memory circuit.
JP18145982U 1982-11-30 1982-11-30 Programmable timing generation circuit Pending JPS5986742U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18145982U JPS5986742U (en) 1982-11-30 1982-11-30 Programmable timing generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18145982U JPS5986742U (en) 1982-11-30 1982-11-30 Programmable timing generation circuit

Publications (1)

Publication Number Publication Date
JPS5986742U true JPS5986742U (en) 1984-06-12

Family

ID=30393201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18145982U Pending JPS5986742U (en) 1982-11-30 1982-11-30 Programmable timing generation circuit

Country Status (1)

Country Link
JP (1) JPS5986742U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170780U (en) * 1984-10-15 1986-05-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170780U (en) * 1984-10-15 1986-05-14

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