JPS59118007U - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPS59118007U JPS59118007U JP850883U JP850883U JPS59118007U JP S59118007 U JPS59118007 U JP S59118007U JP 850883 U JP850883 U JP 850883U JP 850883 U JP850883 U JP 850883U JP S59118007 U JPS59118007 U JP S59118007U
- Authority
- JP
- Japan
- Prior art keywords
- output
- output circuit
- output data
- target
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control By Computers (AREA)
- Programmable Controllers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例の出力回路図、第２図のデー
タとレディ相互間のタイミング関係を示すタイムチャー
ト図、第３図は第２図の拡張例を示すタイムチャート図
である。
１・・・マイクロコンピュータ、２・・・出力回路、３
・・・出力対象装置、２５・・・インバータ。FIG. 1 is an output circuit diagram of an embodiment of the present invention, FIG. 2 is a time chart showing the timing relationship between the data and the ready, and FIG. 3 is a time chart showing an extended example of FIG. 2. . 1... Microcomputer, 2... Output circuit, 3
... Output target device, 25... Inverter.
Claims (1)
に出力されるマイクロコンピュータ制御の装置において
、出力データを出力対象に出力するに際し、出力データ
と出力データ確立信号間のタイミングをプログラマブル
タイマーにより可変とすることを特徴とした出力回路。A microcomputer-controlled device in which output data is output to an output target by a software program, characterized in that when outputting the output data to the output target, the timing between the output data and the output data establishment signal is made variable by a programmable timer. output circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP850883U JPS59118007U (en) | 1983-01-26 | 1983-01-26 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP850883U JPS59118007U (en) | 1983-01-26 | 1983-01-26 | Output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59118007U true JPS59118007U (en) | 1984-08-09 |
Family
ID=30139996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP850883U Pending JPS59118007U (en) | 1983-01-26 | 1983-01-26 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59118007U (en) |
-
1983
- 1983-01-26 JP JP850883U patent/JPS59118007U/en active Pending
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