JPS5888411U

JPS5888411U - AC signal generator

Info

Publication number: JPS5888411U
Application number: JP18419781U
Authority: JP
Inventors: 美昭田中; 大槻　善樹
Original assignee: 日本ビクター株式会社
Priority date: 1981-12-10
Filing date: 1981-12-10
Publication date: 1983-06-15

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案信号発生器の一実施例のブロック系統図
、第２図は正弦波信号とデータとの関係を示す図、第３
図は第１図中メモリの具体的ブロック系統図である。１・・・クロック信号発生器、２〜４・・・カウンタ、
５・・・リード・オンリ・メモリ、７・・・メモリ、８
・・・Ｄ／Ａ変換器、９・・・中央処理制御装置、１０
・・・ＤＣ成分除去回路、１１・・・出力端子。Fig. 1 is a block system diagram of one embodiment of the signal generator of the present invention, Fig. 2 is a diagram showing the relationship between a sine wave signal and data, and Fig. 3 is a diagram showing the relationship between a sine wave signal and data.
The figure is a concrete block system diagram of the memory in FIG. 1. 1... Clock signal generator, 2-4... Counter,
5...Read-only memory, 7...Memory, 8
...D/A converter, 9...Central processing control unit, 10
...DC component removal circuit, 11...output terminal.

Claims

[Scope of utility model registration request]

(1) A circuit that generates a clock pulse, which is supplied with the clock pulse, whose frequency division ratio is varied by an external control signal, and which divides the clock pulse at a frequency division ratio that corresponds to the control signal. a first counter; a second counter that is supplied with the output of the first counter and outputs an address signal at a speed corresponding to the assimilation; and a second counter that outputs an address signal at a speed corresponding to the assimilation; Data consisting of two types of data for the negative level of the AC signal is stored in memory corresponding to the address signal for a predetermined period, and is output at a speed corresponding to the output speed of the address signal. An alternating current signal generator comprising a memory circuit that repeatedly extracts a set of data in a time-division manner, and a circuit that converts the data from the memory circuit from D/A to obtain an alternating current signal.

(2) the memory circuit includes a read-only memory that stores the data and is supplied with the address signal;
first and second memories respectively storing one data and the other data of the data from the read-only memory at two time-shifted timings that are synchronized with the address signal; and a third memory that stores the one data from the first memory when the second memory stores the other data, and simultaneously stores the two types of data from the second and third memories. An alternating current signal generator according to claim 1, which is configured to read data as a set.