JPS58140599U - Dynamic random access memory control circuit - Google Patents

Dynamic random access memory control circuit

Info

Publication number
JPS58140599U
JPS58140599U JP3392782U JP3392782U JPS58140599U JP S58140599 U JPS58140599 U JP S58140599U JP 3392782 U JP3392782 U JP 3392782U JP 3392782 U JP3392782 U JP 3392782U JP S58140599 U JPS58140599 U JP S58140599U
Authority
JP
Japan
Prior art keywords
control circuit
random access
dynamic random
memory control
access memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3392782U
Other languages
Japanese (ja)
Inventor
茂樹 青木
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP3392782U priority Critical patent/JPS58140599U/en
Publication of JPS58140599U publication Critical patent/JPS58140599U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案の一実施例のメモリ制御回路のブロック図で
ある。 １・・・プロセッサのパスライン、２・・・アドレスラ
イン（Ａｏ〜Ａ１５）、３・・・アドレスレシーバ、４
・・・アドレスマルチプレクサ、５・・・ダイナミック
ＲＡＭ。 ６・・・クロック１．７・・・クロック、２．８・・・
クロックレシーバ、９・・・リフレッシュカウンタ、１
０・・・リフレッシュアドレスカウンタ、１１・・・リ
フレッシュリクエスト線、１２・・・メモリ制御１１３
・・・メモリリード、１４・・・メモリライト、１５・
・・メモリコントロールレシーバ、１６・・・メモリア
クセス・リフレッシュ動作制御回路、１７・・・メモリ
制御タイミングジェネレータ、１８・・・データ・レシ
ーバ／ドライバ、１９・・・データライン、２０・・・
データアウト。The figure is a block diagram of a memory control circuit according to an embodiment of the present invention. 1... Processor pass line, 2... Address line (Ao to A15), 3... Address receiver, 4
... Address multiplexer, 5... Dynamic RAM. 6...Clock 1.7...Clock, 2.8...
Clock receiver, 9... Refresh counter, 1
0... Refresh address counter, 11... Refresh request line, 12... Memory control 113
...Memory read, 14...Memory write, 15.
...Memory control receiver, 16...Memory access/refresh operation control circuit, 17...Memory control timing generator, 18...Data receiver/driver, 19...Data line, 20...
Data out.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リフレッシュ制御を要するダイナミックランダムアクセ
スメモリ制御回路において、アクセスを行なうプロセッ
サの多相基本クロックをリフレッシュ制御回路に用いる
ことにより、リフレッシュ動作をプロセッサのメモリに
対するリードライトアクセス時間以外に実施することを
特徴とするダイナミックランダムアクセスメモリ制御回
路。A dynamic random access memory control circuit that requires refresh control is characterized in that by using a multiphase basic clock of a processor that performs access in the refresh control circuit, a refresh operation is performed outside the read/write access time of the processor to the memory. Dynamic random access memory control circuit.
JP3392782U 1982-03-12 1982-03-12 Dynamic random access memory control circuit Pending JPS58140599U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3392782U JPS58140599U (en) 1982-03-12 1982-03-12 Dynamic random access memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3392782U JPS58140599U (en) 1982-03-12 1982-03-12 Dynamic random access memory control circuit

Publications (1)

Publication Number Publication Date
JPS58140599U true JPS58140599U (en) 1983-09-21

Family

ID=30045451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3392782U Pending JPS58140599U (en) 1982-03-12 1982-03-12 Dynamic random access memory control circuit

Country Status (1)

Country Link
JP (1) JPS58140599U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362593A (en) * 1991-06-10 1992-12-15 Agency Of Ind Science & Technol Refreshing control system for dram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362593A (en) * 1991-06-10 1992-12-15 Agency Of Ind Science & Technol Refreshing control system for dram

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