JPS59118048U - Bidirectional direct memory access transfer circuit - Google Patents
Bidirectional direct memory access transfer circuitInfo
- Publication number
- JPS59118048U JPS59118048U JP990883U JP990883U JPS59118048U JP S59118048 U JPS59118048 U JP S59118048U JP 990883 U JP990883 U JP 990883U JP 990883 U JP990883 U JP 990883U JP S59118048 U JPS59118048 U JP S59118048U
- Authority
- JP
- Japan
- Prior art keywords
- memory access
- direct memory
- transfer circuit
- bidirectional direct
- access transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Small-Scale Networks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来のＤＭＡＣを採用した回路の構成図、第
２図は、本考案の双方向ＤＭＡ転送回路の実施例の回路
構成図、第３図は、第２図のタイムチャートである。
２・・・ＤＭＡ制御信号発生回路、４・・・転送アドレ
ス発生回路、１３・・・ＨＯＬＤ要求信号、１４Ａ。
１４Ｂ・・・ＨＯＬＤ応答信号。FIG. 1 is a block diagram of a circuit employing a conventional DMAC, FIG. 2 is a circuit block diagram of an embodiment of the bidirectional DMA transfer circuit of the present invention, and FIG. 3 is a time chart of FIG. 2. . 2...DMA control signal generation circuit, 4...Transfer address generation circuit, 13...HOLD request signal, 14A. 14B...HOLD response signal.
Claims (1)
系の誉れぞれに設けられた、制御情報格納用メモリ間で
の制御情報の転送を、マイクロプロセッサをホールドさ
せた状態でシステムバスを占有し、転送に必要な制御信
号を発生することによって、メモリ間で直接実行させる
ことが可能で。 あり、ソフトウェアの介在なしに簡易なハードウェアに
て構成できるように形成したことを特徴とする双方向ダ
イレクトメモリアクセス転送回路。[Claim for Utility Model Registration] In a microprocessor application system, the transfer of control information between memory for storing control information provided in each of the different control systems is carried out using the system bus while the microprocessor is held. It is possible to execute directly between memories by occupying the memory and generating the control signals necessary for the transfer. 1. A bidirectional direct memory access transfer circuit characterized in that it is formed so that it can be configured with simple hardware without the intervention of software.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP990883U JPS59118048U (en) | 1983-01-28 | 1983-01-28 | Bidirectional direct memory access transfer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP990883U JPS59118048U (en) | 1983-01-28 | 1983-01-28 | Bidirectional direct memory access transfer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59118048U true JPS59118048U (en) | 1984-08-09 |
Family
ID=30141355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP990883U Pending JPS59118048U (en) | 1983-01-28 | 1983-01-28 | Bidirectional direct memory access transfer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59118048U (en) |
-
1983
- 1983-01-28 JP JP990883U patent/JPS59118048U/en active Pending
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