JPS60164258U - data transfer control device - Google Patents
data transfer control deviceInfo
- Publication number
- JPS60164258U JPS60164258U JP4735784U JP4735784U JPS60164258U JP S60164258 U JPS60164258 U JP S60164258U JP 4735784 U JP4735784 U JP 4735784U JP 4735784 U JP4735784 U JP 4735784U JP S60164258 U JPS60164258 U JP S60164258U
- Authority
- JP
- Japan
- Prior art keywords
- transfer control
- data transfer
- memory
- control device
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来装置例を示す図、第2図は本考案の一実施
例を示す電気的構成図、第3図はデータ転送制御回路の
具体的構成を示す図、第4図は各部の動作波形を示すタ
イミングチャートである。
1.2・・・・・・CPU、3,11・・・・・・メモ
リ、4゜13・・・・・・データ転送制御回路、5,6
・・・・・・データバッファ、12・・・・・・クロッ
ク発生器、14・・・・・・アドレスカウンタ、21,
22.24〜27・・・・・・フリップフロップ、23
・・・・・・インバータ、28.29・・・・・・オア
ゲート、30,31・・・・・・ワンショット回路。Fig. 1 is a diagram showing an example of a conventional device, Fig. 2 is an electrical configuration diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing a specific configuration of a data transfer control circuit, and Fig. 4 is a diagram showing each part. 5 is a timing chart showing operation waveforms. 1.2...CPU, 3,11...Memory, 4゜13...Data transfer control circuit, 5,6
...Data buffer, 12...Clock generator, 14...Address counter, 21,
22.24-27...Flip-flop, 23
...Inverter, 28.29...OR gate, 30,31...One-shot circuit.
Claims (2)
送を行う場合において、これらCPUの間に設けられた
データの書込みと読出しの可能なメーモリと、該メモリ
にアドレスを与えるアドレスカウンタと、基準クロック
を発生するクロック発生器と、該クロック発生器の出力
及び第1及び第2のCPUからのり多エスト信号を受け
、前記メモリへのデータの書込みと読出しの制御を行う
と共に、前記アト、レスカウンタへのカウント制御信号
及び第1及び第2のCPUヘアクツリッジ信号を与える
データ転送制御回路とにより構成され、第1及び第2の
CPUから同時にフリエスト信号が来た場合は、前記ク
ロック発生器の出力クロックの立上りと立下りでこれら
リクエスト信号を振り分けるようにしたことを特徴とす
るデータ転送制御装置。(1) When transferring data between a first CPU and a second CPU, a memory provided between these CPUs that can write and read data, and an address that gives an address to the memory. a counter, a clock generator that generates a reference clock, and receives an output of the clock generator and a multi-est signal from the first and second CPUs, and controls writing and reading of data to the memory; and a data transfer control circuit that provides a count control signal to the at/res counter and a first and second CPU haircut signal, and when the first and second CPUs receive the first signal simultaneously, A data transfer control device characterized in that these request signals are distributed according to the rising and falling edges of a generator's output clock.
ことを特徴とする実用新案登録請求の範囲第1項記載の
データ転送制御装置。(2) The data transfer control device according to claim 1, wherein a FIFOH type RAM is used as the memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4735784U JPS60164258U (en) | 1984-03-31 | 1984-03-31 | data transfer control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4735784U JPS60164258U (en) | 1984-03-31 | 1984-03-31 | data transfer control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60164258U true JPS60164258U (en) | 1985-10-31 |
Family
ID=30562607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4735784U Pending JPS60164258U (en) | 1984-03-31 | 1984-03-31 | data transfer control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60164258U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000163246A (en) * | 1998-11-25 | 2000-06-16 | Hitachi Ltd | Storage device subsystem having fifo function |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5394745A (en) * | 1977-01-31 | 1978-08-19 | Copal Co Ltd | Method of processing data |
JPS57152057A (en) * | 1981-03-14 | 1982-09-20 | Toshiba Corp | Memory device |
-
1984
- 1984-03-31 JP JP4735784U patent/JPS60164258U/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5394745A (en) * | 1977-01-31 | 1978-08-19 | Copal Co Ltd | Method of processing data |
JPS57152057A (en) * | 1981-03-14 | 1982-09-20 | Toshiba Corp | Memory device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000163246A (en) * | 1998-11-25 | 2000-06-16 | Hitachi Ltd | Storage device subsystem having fifo function |
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