JPS6124900U - selection circuit - Google Patents
selection circuitInfo
- Publication number
- JPS6124900U JPS6124900U JP10532284U JP10532284U JPS6124900U JP S6124900 U JPS6124900 U JP S6124900U JP 10532284 U JP10532284 U JP 10532284U JP 10532284 U JP10532284 U JP 10532284U JP S6124900 U JPS6124900 U JP S6124900U
- Authority
- JP
- Japan
- Prior art keywords
- selection circuit
- register
- chip
- selection signal
- selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の選択回路を含む計算機システムの概略
図、第2図は制御レジスタの構成例を示す図、第3図は
本考案の実施例における制御レジスタ及び比較回路の詳
細を示す図である。FIG. 1 is a schematic diagram of a computer system including a selection circuit of the present invention, FIG. 2 is a diagram showing an example of the configuration of a control register, and FIG. 3 is a diagram showing details of the control register and comparison circuit in an embodiment of the present invention. It is.
Claims (1)
計算機システムにおいて上記メモリ・チツブ1こチツプ
選択信号を供給する選択回路であって、上記チップ毎に
レジスタと比較回路とを有し、上記レジスタは上記処理
装置によりデータを設定することができ、上記比較回路
は上記処理装、置から供給されるアクセス情報と上記レ
ジスタに設定された情報とを比較して条件が満足されれ
ば上記チップの1つに選択信号を出力し、上記レジスタ
の設定内容に依存してアドレスに対するチップ選択信号
の関係が可変になるように構成された選択回路。A selection circuit for supplying a chip selection signal to one of the memory chips in a computer system having a central processing unit and a plurality of memory chips, the selection circuit having a register and a comparison circuit for each of the chips; The data can be set by the processing device, and the comparison circuit compares the access information supplied from the processing device and the information set in the register, and if the conditions are satisfied, the data is set in the chip. A selection circuit configured to output a selection signal to one of the registers and to make the relationship between the chip selection signal and the address variable depending on the setting contents of the register.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10532284U JPS6124900U (en) | 1984-07-13 | 1984-07-13 | selection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10532284U JPS6124900U (en) | 1984-07-13 | 1984-07-13 | selection circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6124900U true JPS6124900U (en) | 1986-02-14 |
Family
ID=30664655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10532284U Pending JPS6124900U (en) | 1984-07-13 | 1984-07-13 | selection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6124900U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS584466A (en) * | 1981-06-30 | 1983-01-11 | Fujitsu Ltd | Control system for storage constitution |
-
1984
- 1984-07-13 JP JP10532284U patent/JPS6124900U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS584466A (en) * | 1981-06-30 | 1983-01-11 | Fujitsu Ltd | Control system for storage constitution |
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