JPS59107800U - Computer system function check device - Google Patents
Computer system function check deviceInfo
- Publication number
- JPS59107800U JPS59107800U JP56683U JP56683U JPS59107800U JP S59107800 U JPS59107800 U JP S59107800U JP 56683 U JP56683 U JP 56683U JP 56683 U JP56683 U JP 56683U JP S59107800 U JPS59107800 U JP S59107800U
- Authority
- JP
- Japan
- Prior art keywords
- computer system
- dma
- check device
- data
- system function
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の機能チェック装置を示す構成図、第２図
は本考案の全体構成図、第３図は第２図における機能チ
ェック装置の一実施例を示す要部ブロック図である。
１・・・・・・ｃｐｕ、 ２・・・・・・メモリ、４・
・・・・・共通バス、７・・・・・・機能チェック装置
、８・・・・・・転送要求部、９・・・・・・異常チェ
ック部、１０・・・・・・アドレスデータ発生部、１１
・・・・・・データ発生部、１２・・・・・・データチ
ェック部、１３・・・・・・異常表示部。FIG. 1 is a block diagram showing a conventional function check device, FIG. 2 is a general block diagram of the present invention, and FIG. 3 is a block diagram of essential parts of an embodiment of the function check device shown in FIG. 1... CPU, 2... Memory, 4...
... Common bus, 7 ... Function check device, 8 ... Transfer request section, 9 ... Abnormality check section, 10 ... Address data Occurrence part, 11
. . . Data generation section, 12 . . . Data check section, 13 . . . Abnormality display section.
Claims (1)
ュータシステムのＣＰＵへのＤＭＡ要：［−設定される
頻度で行ないＤＭＡ動作の可否チェック及びＤＭＡ許可
信号が与えられる毎にメモリに対して設定されるメモリ
アドレスデータと書込みデータを発生又はメモリアドレ
スデータ発生と該メモリからの読出しデータの正誤チェ
ック手段を持つＤＭＡ動作を行なうＤＭＡコントローラ
を備えたことを特徴とするコンピュータシステムの機能
チェック装置。Connected to a common bus of a computer system, DMA request to the CPU of the computer system: [- Checks whether or not DMA operation is possible at a set frequency, and sets a memory address for the memory every time a DMA permission signal is given. A function checking device for a computer system, comprising a DMA controller that performs a DMA operation and has means for generating data and write data, generating memory address data, and checking correctness of data read from the memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56683U JPS59107800U (en) | 1983-01-07 | 1983-01-07 | Computer system function check device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56683U JPS59107800U (en) | 1983-01-07 | 1983-01-07 | Computer system function check device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59107800U true JPS59107800U (en) | 1984-07-20 |
Family
ID=30132316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56683U Pending JPS59107800U (en) | 1983-01-07 | 1983-01-07 | Computer system function check device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59107800U (en) |
-
1983
- 1983-01-07 JP JP56683U patent/JPS59107800U/en active Pending
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