JPS5953443U - data transfer device - Google Patents

data transfer device

Info

Publication number
JPS5953443U
JPS5953443U JP14938082U JP14938082U JPS5953443U JP S5953443 U JPS5953443 U JP S5953443U JP 14938082 U JP14938082 U JP 14938082U JP 14938082 U JP14938082 U JP 14938082U JP S5953443 U JPS5953443 U JP S5953443U
Authority
JP
Japan
Prior art keywords
error processing
data transfer
transfer device
error
processing means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14938082U
Other languages
Japanese (ja)
Other versions
JPS6217877Y2 (en
Inventor
勝 石田
樽門　豊
Original Assignee
株式会社島津製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社島津製作所 filed Critical 株式会社島津製作所
Priority to JP14938082U priority Critical patent/JPS5953443U/en
Publication of JPS5953443U publication Critical patent/JPS5953443U/en
Application granted granted Critical
Publication of JPS6217877Y2 publication Critical patent/JPS6217877Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例のブロック回路図、第２図は本
考案の他の実施例のブロック回路図である。FIG. 1 is a block circuit diagram of an embodiment of the present invention, and FIG. 2 is a block circuit diagram of another embodiment of the present invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＤＭＡ方式によりデータ転送を行うコンピュータシステ
ムにおけるデータ転送装置において、ホストＣＰＵと外
部デバイスとの間にＣＲＣエラー等のエラー処理手段を
介在させ、ホストＣＰＵからエラー処理手段には予めシ
ーク命令や読み出し／書き込み命令、ワード数、リトラ
イ回数等のエラー処理プログラムが与えられ、データ転
送実行中にエラーが発生したときにはエラー処理プログ
ラムに従ってエラー処理手段かりトライ回数だけエラー
処理することを特徴とするデータ転送装置。In a data transfer device in a computer system that transfers data using the DMA method, an error processing means such as a CRC error is interposed between the host CPU and an external device, and the host CPU sends a seek command or read/write to the error processing means in advance. A data transfer device characterized in that an error processing program including instructions, number of words, number of retries, etc. is given, and when an error occurs during execution of data transfer, error processing is performed by an error processing means for the number of tries according to the error processing program.
JP14938082U 1982-09-30 1982-09-30 data transfer device Granted JPS5953443U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14938082U JPS5953443U (en) 1982-09-30 1982-09-30 data transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14938082U JPS5953443U (en) 1982-09-30 1982-09-30 data transfer device

Publications (2)

Publication Number Publication Date
JPS5953443U true JPS5953443U (en) 1984-04-07
JPS6217877Y2 JPS6217877Y2 (en) 1987-05-08

Family

ID=30331615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14938082U Granted JPS5953443U (en) 1982-09-30 1982-09-30 data transfer device

Country Status (1)

Country Link
JP (1) JPS5953443U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5528194A (en) * 1978-08-21 1980-02-28 Omron Tateisi Electronics Co Initial program load system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5528194A (en) * 1978-08-21 1980-02-28 Omron Tateisi Electronics Co Initial program load system

Also Published As

Publication number Publication date
JPS6217877Y2 (en) 1987-05-08

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