JPS59138928U - process output circuit - Google Patents
process output circuitInfo
- Publication number
- JPS59138928U JPS59138928U JP3138283U JP3138283U JPS59138928U JP S59138928 U JPS59138928 U JP S59138928U JP 3138283 U JP3138283 U JP 3138283U JP 3138283 U JP3138283 U JP 3138283U JP S59138928 U JPS59138928 U JP S59138928U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- interface circuit
- circuit
- output circuit
- process output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のプロセス出力回路のブロック図、第２図
はこの考案の一実施例を示すプロセス出力回路のブロッ
ク図である。
１・・・中央処理装置（ＣＰＵ）、２・・・バス、２・
・・プロセス出力回路、４・・・メモリ、５．７・・・
インターフェイス回路、６・・・制御回路、７・・・信
号チェック回路。なお、各図中、同一符号は同一、また
は相当部分を示すものとする。FIG. 1 is a block diagram of a conventional process output circuit, and FIG. 2 is a block diagram of a process output circuit showing an embodiment of this invention. 1...Central processing unit (CPU), 2...Bus, 2.
...Process output circuit, 4...Memory, 5.7...
Interface circuit, 6... control circuit, 7... signal check circuit. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
て出力する第１インターフェイス回路を有するプロセス
出力回路において、上記第１インターフェイス回路の出
力信号を論理レベルの信号に変換する第２インターフェ
イス回路と、上記第１インターフェイス回路の入力信号
と上記第２インターフェイス回路の出力信号との一致を
調べ、不一致が検出されたときは上記出力信号に異常が
あることを示す信号を出力する信号チェック回路とを備
えたことを特徴とするプロセス出力回路。A process output circuit having a first interface circuit that converts a logic level signal to a signal level of a process device and outputs the signal, a second interface circuit that converts an output signal of the first interface circuit to a logic level signal; and a signal check circuit that checks whether the input signal of the first interface circuit matches the output signal of the second interface circuit and outputs a signal indicating that there is an abnormality in the output signal when a mismatch is detected. A process output circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3138283U JPS59138928U (en) | 1983-03-02 | 1983-03-02 | process output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3138283U JPS59138928U (en) | 1983-03-02 | 1983-03-02 | process output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59138928U true JPS59138928U (en) | 1984-09-17 |
Family
ID=30162230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3138283U Pending JPS59138928U (en) | 1983-03-02 | 1983-03-02 | process output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59138928U (en) |
-
1983
- 1983-03-02 JP JP3138283U patent/JPS59138928U/en active Pending
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