JPS60112857U - Data transfer circuit between microprocessors - Google Patents
Data transfer circuit between microprocessorsInfo
- Publication number
- JPS60112857U JPS60112857U JP20192683U JP20192683U JPS60112857U JP S60112857 U JPS60112857 U JP S60112857U JP 20192683 U JP20192683 U JP 20192683U JP 20192683 U JP20192683 U JP 20192683U JP S60112857 U JPS60112857 U JP S60112857U
- Authority
- JP
- Japan
- Prior art keywords
- microprocessors
- circuit
- data transfer
- bus
- transfer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面はこの考案の従来技術および実施例を示すものであ
って、第１図は従来技術、第２図は実施例を示すブロッ
ク図である。
第１図において１．２． ３はそれぞれ第１、第２、第
３のマイクロプロセッサ、４はメモリ、５ａおよび５ｂ
はそれぞれプライオテイエンコーダおよびデコーダ（優
先度判定回路）、７はフリップフロップ回路（バスロッ
ク回路）、８はラッチ回路（保持回路）である。The drawings show a prior art and an embodiment of this invention, with FIG. 1 being a block diagram showing the prior art and FIG. 2 being a block diagram showing the embodiment. In Figure 1, 1.2. 3 are first, second, and third microprocessors, respectively; 4 is memory; 5a and 5b;
are a priority encoder and a decoder (priority determination circuit), 7 is a flip-flop circuit (bus lock circuit), and 8 is a latch circuit (holding circuit).
Claims (1)
で接続し、前記複数のマイクロプロセッサからのバス占
有要求信号を優先度の高い前記マイクロプロセッサの順
に優先度判定回路の入力に接続し、この優先度判定回路
の出力をバス占有許可信号として優先度の高い順に前記
マイクロプロ、 セッサに接続してなるマイクロプロセ
ッサ間のデータ転送回路において、前記各マイクロプロ
セッサのバス占有信号および前記マイクロプロセッサの
バス占有終了信号を入力するバスロック回路を設け、前
記優先度判定回路の出力を入力する保持回路の制御入力
として前記バスロック回路の出力を接続し、前記保持回
路の出力は優先度の高い順に前記マイクロプロセッサに
接続してなる前記マイクロプロセッサ間のデータ転送回
路。 （２）前記優先度判定回路はプライオリティエンコーダ
とデコーダとを接続してなる実用新案登録請求の範囲第
１項記載のマイクロプロセッサ間のデータ転送回路。 （３）前記バスロック回路はフリップフロップである実
用新案登録請求の範囲第１項記載のマイクロプロセッサ
間のデータ転送回路。[Claims for Utility Model Registration] A plurality of microprocessors and memories are connected via a system bus, and bus occupancy request signals from the plurality of microprocessors are connected to inputs of a priority determination circuit in the order of the microprocessors having the highest priority. The output of this priority determination circuit is used as a bus occupancy permission signal to transmit the bus occupancy signal of each microprocessor and the microprocessor in an inter-microprocessor data transfer circuit which is connected to the microprocessor and processor in descending order of priority. A bus lock circuit is provided to input a bus occupancy end signal of the processor, and the output of the bus lock circuit is connected as a control input of a holding circuit to which the output of the priority determination circuit is input. A data transfer circuit between the microprocessors is connected to the microprocessors in descending order. (2) The data transfer circuit between microprocessors according to claim 1, wherein the priority determination circuit is formed by connecting a priority encoder and a decoder. (3) The data transfer circuit between microprocessors according to claim 1, wherein the bus lock circuit is a flip-flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20192683U JPS60112857U (en) | 1983-12-29 | 1983-12-29 | Data transfer circuit between microprocessors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20192683U JPS60112857U (en) | 1983-12-29 | 1983-12-29 | Data transfer circuit between microprocessors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60112857U true JPS60112857U (en) | 1985-07-31 |
Family
ID=30764166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20192683U Pending JPS60112857U (en) | 1983-12-29 | 1983-12-29 | Data transfer circuit between microprocessors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60112857U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5258432A (en) * | 1975-11-10 | 1977-05-13 | Nec Corp | Common bus control circuit |
| JPS5335447A (en) * | 1976-09-14 | 1978-04-01 | Oki Electric Ind Co Ltd | Multi processor system |
| JPS54541A (en) * | 1977-06-03 | 1979-01-05 | Toshiba Corp | Computer compoiste system |
-
1983
- 1983-12-29 JP JP20192683U patent/JPS60112857U/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5258432A (en) * | 1975-11-10 | 1977-05-13 | Nec Corp | Common bus control circuit |
| JPS5335447A (en) * | 1976-09-14 | 1978-04-01 | Oki Electric Ind Co Ltd | Multi processor system |
| JPS54541A (en) * | 1977-06-03 | 1979-01-05 | Toshiba Corp | Computer compoiste system |
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