JPS5996610U - Bus abnormality detection circuit - Google Patents

Bus abnormality detection circuit

Info

Publication number
JPS5996610U
JPS5996610U JP19352482U JP19352482U JPS5996610U JP S5996610 U JPS5996610 U JP S5996610U JP 19352482 U JP19352482 U JP 19352482U JP 19352482 U JP19352482 U JP 19352482U JP S5996610 U JPS5996610 U JP S5996610U
Authority
JP
Japan
Prior art keywords
abnormality detection
detection circuit
bus
bus abnormality
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19352482U
Other languages
Japanese (ja)
Inventor
周 吉田
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP19352482U priority Critical patent/JPS5996610U/en
Publication of JPS5996610U publication Critical patent/JPS5996610U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路図である。　　　
３１．３２・・・バッファ、６１．６２・・・排他的論
理和回路、７０・・・バス。FIG. 1 is a circuit diagram showing an embodiment of the present invention.
31.32... Buffer, 61.62... Exclusive OR circuit, 70... Bus.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] バスにデジタル信号を供給する線路に挿入しである緩衝
回路と、こめ緩衝回路の入力と出力とを比較して前記入
力の論理値に対する前記出力の論理値が予め定めた関係
にないとき所定の異常検出信号を出力す回路とからなる
バス異常検出回路。A buffer circuit inserted into the line that supplies digital signals to the bus compares the input and output of the buffer circuit, and when the logical value of the output with respect to the logical value of the input does not have a predetermined relationship, a predetermined A bus abnormality detection circuit consisting of a circuit that outputs an abnormality detection signal.
JP19352482U 1982-12-21 1982-12-21 Bus abnormality detection circuit Pending JPS5996610U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19352482U JPS5996610U (en) 1982-12-21 1982-12-21 Bus abnormality detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19352482U JPS5996610U (en) 1982-12-21 1982-12-21 Bus abnormality detection circuit

Publications (1)

Publication Number Publication Date
JPS5996610U true JPS5996610U (en) 1984-06-30

Family

ID=30416210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19352482U Pending JPS5996610U (en) 1982-12-21 1982-12-21 Bus abnormality detection circuit

Country Status (1)

Country Link
JP (1) JPS5996610U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0934749A (en) * 1995-07-19 1997-02-07 Nec Corp Fault diagnostic method for bus interface circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0934749A (en) * 1995-07-19 1997-02-07 Nec Corp Fault diagnostic method for bus interface circuit

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