JPS5980849U - DMA device - Google Patents

DMA device

Info

Publication number
JPS5980849U
JPS5980849U JP17333882U JP17333882U JPS5980849U JP S5980849 U JPS5980849 U JP S5980849U JP 17333882 U JP17333882 U JP 17333882U JP 17333882 U JP17333882 U JP 17333882U JP S5980849 U JPS5980849 U JP S5980849U
Authority
JP
Japan
Prior art keywords
signal
dma
circuit
dma device
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17333882U
Other languages
Japanese (ja)
Inventor
和山　幸夫
八島　一成
Original Assignee
株式会社明電舎
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社明電舎 filed Critical 株式会社明電舎
Priority to JP17333882U priority Critical patent/JPS5980849U/en
Publication of JPS5980849U publication Critical patent/JPS5980849U/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Bus Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＤＭＡ装置を示した構成図、第２図は本
考案の一実施例を示した構成図である。 １はＤＭＡ装置、２はメモリ、１１．１２はパスドライ
バー、１３．１４はＤＭＡ信号出力回路、１５．１６は
パスレシーバ、１７．１８はパリティジェネレータ回路
、１９．２０はパリティチェック回路。FIG. 1 is a block diagram showing a conventional DMA device, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1 is a DMA device, 2 is a memory, 11.12 is a path driver, 13.14 is a DMA signal output circuit, 15.16 is a path receiver, 17.18 is a parity generator circuit, and 19.20 is a parity check circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）ＤＭＡ信号をアドレス部・データ部の夫々のハス
ドライバーを介してパスに出力するＤＭＡ装置において
、前記アドレス部とデータ部を夫々、ＤＭＡ信号出力回
路と、前記ハスドライバーの出力信号を入力するハスレ
シーバと、このハスレシーバからの信号とＤＭＡ信号出
力回路からの信号とを比較する比較回路とて構成し備え
たことを特徴とするＤＭＡ装置。 ｆ２）ＤＭＡ信号出力回路からの信号をパリティジェネ
レータ回路を介して比較回路に出力するようにしたこと
を特徴とする実用新案登録請求の範囲第（１）項記載の
ＤＭＡ装置。(1) In a DMA device that outputs a DMA signal to a path via a lotus driver in each of the address section and data section, the address section and the data section are respectively inputted to a DMA signal output circuit and the output signal of the lotus driver. What is claimed is: 1. A DMA device comprising: a hash receiver, and a comparison circuit that compares a signal from the hash receiver with a signal from a DMA signal output circuit. f2) The DMA device according to claim (1) of the utility model registration, characterized in that the signal from the DMA signal output circuit is output to the comparison circuit via a parity generator circuit.
JP17333882U 1982-11-16 1982-11-16 DMA device Pending JPS5980849U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17333882U JPS5980849U (en) 1982-11-16 1982-11-16 DMA device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17333882U JPS5980849U (en) 1982-11-16 1982-11-16 DMA device

Publications (1)

Publication Number Publication Date
JPS5980849U true JPS5980849U (en) 1984-05-31

Family

ID=30377633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17333882U Pending JPS5980849U (en) 1982-11-16 1982-11-16 DMA device

Country Status (1)

Country Link
JP (1) JPS5980849U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS548426A (en) * 1977-06-22 1979-01-22 Fujitsu Ltd Block erroe correction device
JPS5413236A (en) * 1977-07-01 1979-01-31 Hitachi Ltd Bus control system
JPS55157022A (en) * 1979-05-24 1980-12-06 Matsushita Electric Ind Co Ltd Output circuit for microcomputer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS548426A (en) * 1977-06-22 1979-01-22 Fujitsu Ltd Block erroe correction device
JPS5413236A (en) * 1977-07-01 1979-01-31 Hitachi Ltd Bus control system
JPS55157022A (en) * 1979-05-24 1980-12-06 Matsushita Electric Ind Co Ltd Output circuit for microcomputer

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