JPS59100346U - Microprogram operation storage device - Google Patents
Microprogram operation storage deviceInfo
- Publication number
- JPS59100346U JPS59100346U JP19489882U JP19489882U JPS59100346U JP S59100346 U JPS59100346 U JP S59100346U JP 19489882 U JP19489882 U JP 19489882U JP 19489882 U JP19489882 U JP 19489882U JP S59100346 U JPS59100346 U JP S59100346U
- Authority
- JP
- Japan
- Prior art keywords
- storage device
- operation storage
- memory register
- microprogram
- microprogram operation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はマイクロプロセッサを搭載したインターフェイ
スとそれを使ったＣＰＵシステムの構成図、第２図は従
来例のマイクロプログラム動作記憶装置とインターフェ
イスの構成図、第３図は本考案の一実施例のマイクロプ
ログラム動作記憶装置とインターフェイスの構成図、第
４図は同じく本考案によるマイクロプログラム動作記憶
装置の内部構成図である。
８・・・マイクロプロセッサ、１３川インターフエイス
、１７・・・コントロール回路、２０・・・マイクロプ
ロセッサ、２６・・・表示器、６０・・・メモリタイミ
ング回路、６４・・・メモリ信号。Fig. 1 is a block diagram of an interface equipped with a microprocessor and a CPU system using it, Fig. 2 is a block diagram of a conventional microprogram operating storage device and an interface, and Fig. 3 is a block diagram of an embodiment of the present invention. FIG. 4 is a diagram showing the internal configuration of the microprogram storage device and the interface according to the present invention. 8...Microprocessor, 13...Control circuit, 20...Microprocessor, 26...Display device, 60...Memory timing circuit, 64...Memory signal.
Claims (1)
クロプロセッサのアドレスバス、データバスの動作をト
レースするマイクロプログラム動作記憶装置で構成され
、該インターフェイスとマイクロプログラム動作記憶装
置はコ・ネクターで接続され、前記マイクロプログラム
動作記憶装置はアドレスメモリレジスタとデータメモリ
レジスタ、リングカウンタＣＰＵバスの入出力コントロ
ール回路を有し、アドレスメモリレジスタ、データメモ
リレジスタおよびその他のマイクロプロセッサ内部レジ
スタの内容をＣＰＵパスを通じてＣＰＵが情報収集でき
るようにしたことを特徴とするマイクロプログラム動作
記憶装置。The interface is configured with a microprogram operation storage device that traces the operations of an address bus and a data bus of an interface microprocessor equipped with a microprocessor, and the interface and the microprogram operation storage device are connected by a connector, and the microprogram operation storage device is connected with a connector. The storage device has an input/output control circuit for an address memory register, a data memory register, and a ring counter CPU bus, and allows the CPU to collect information about the contents of the address memory register, data memory register, and other internal registers of the microprocessor through the CPU path. A microprogram operation storage device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19489882U JPS59100346U (en) | 1982-12-24 | 1982-12-24 | Microprogram operation storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19489882U JPS59100346U (en) | 1982-12-24 | 1982-12-24 | Microprogram operation storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59100346U true JPS59100346U (en) | 1984-07-06 |
Family
ID=30418774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19489882U Pending JPS59100346U (en) | 1982-12-24 | 1982-12-24 | Microprogram operation storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59100346U (en) |
-
1982
- 1982-12-24 JP JP19489882U patent/JPS59100346U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59100346U (en) | Microprogram operation storage device | |
| JPS59113837U (en) | Graphic output device | |
| JPS5837259U (en) | facsimile machine | |
| JPS5851333U (en) | Program processing device | |
| JPS5881654U (en) | arithmetic processing unit | |
| JPS6071956U (en) | Multi-CPU system with version check function | |
| JPS59169651U (en) | Debugging device | |
| JPS6452063U (en) | ||
| JPS59182756U (en) | microcomputer | |
| JPS6095654U (en) | data transfer control device | |
| JPS60144143U (en) | Failure diagnosis device | |
| JPS58183557U (en) | Program execution time measuring device | |
| JPS58118599U (en) | Storage device | |
| JPS6065843U (en) | Memory address expansion circuit | |
| JPS5984627U (en) | Interval timer built into computer | |
| JPS5872800U (en) | Memory protection device for configuration data | |
| JPS60135939U (en) | Processing device runaway detection circuit | |
| JPS6087050U (en) | data transfer control device | |
| JPS59182762U (en) | information processing equipment | |
| JPS5992929U (en) | Memory monitoring device for DMA device | |
| JPS5851359U (en) | Output circuit | |
| JPS5851336U (en) | Direct memory access control circuit | |
| JPS5844642U (en) | Debugging device | |
| JPS6124900U (en) | selection circuit | |
| JPS6071964U (en) | Dual port RAM |