JPS5844642U - Debugging device - Google Patents
Debugging deviceInfo
- Publication number
- JPS5844642U JPS5844642U JP13581881U JP13581881U JPS5844642U JP S5844642 U JPS5844642 U JP S5844642U JP 13581881 U JP13581881 U JP 13581881U JP 13581881 U JP13581881 U JP 13581881U JP S5844642 U JPS5844642 U JP S5844642U
- Authority
- JP
- Japan
- Prior art keywords
- debugging
- memory
- processing unit
- central processing
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例を示す回路ブロック図、第
２図は第１図実施例回路のメモリの空間配置を示す図、
第３図は第、１図実施例回路の動作を説明するためのタ
イミングチャートである。
１：中央処理装置、２：データバス、３・５ニゲ−゛ト
回路、４ニジステムメモリ、６：デバツグ制御メ′モリ
、７：アドレスバス、８：フリップフロップ回路、９：
クロック信号線、１０：シフトレジスタ。FIG. 1 is a circuit block diagram showing an embodiment of this invention, FIG. 2 is a diagram showing the spatial arrangement of the memory of the circuit of the embodiment shown in FIG.
FIG. 3 is a timing chart for explaining the operation of the circuit of the embodiment shown in FIGS. 1: Central processing unit, 2: Data bus, 3.5 Ni gate circuit, 4 Ni system memory, 6: Debug control memory, 7: Address bus, 8: Flip-flop circuit, 9:
Clock signal line, 10: Shift register.
Claims (1)
処理装置を利用して前記システムをデバッグするデバッ
グ装置において、 前記メモリとは空間の異なる、デバッグ用のプログラム
を記憶したデバッグ用メモリと、前記中央処理装置との
結合を前記メモ刀と前記デバッグ用メモリ間で切換える
手段と、デバッグ動作中前記デバッグ用メモリに記憶さ
れたプログラムによりメモリ参照あるいは変更命令とこ
の命令の実行を知らせる出力命令が実行されると前記切
換手段を一時的に前記メモリに切換える回路手段とを備
えたことを特徴とするデバッグ装置。[Claims for Utility Model Registration] A debugging device for debugging a system using the central processing unit of a system comprising a central processing unit and a memory, which stores a debugging program in a space different from that of the memory. means for switching the connection between the debugging memory and the central processing unit between the notepad and the debugging memory; and a means for switching the connection between the debugging memory and the central processing unit; A debugging device comprising circuit means for temporarily switching the switching means to the memory when an output command notifying execution is executed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13581881U JPS5844642U (en) | 1981-09-12 | 1981-09-12 | Debugging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13581881U JPS5844642U (en) | 1981-09-12 | 1981-09-12 | Debugging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5844642U true JPS5844642U (en) | 1983-03-25 |
| JPS625724Y2 JPS625724Y2 (en) | 1987-02-09 |
Family
ID=29929168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13581881U Granted JPS5844642U (en) | 1981-09-12 | 1981-09-12 | Debugging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5844642U (en) |
-
1981
- 1981-09-12 JP JP13581881U patent/JPS5844642U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS625724Y2 (en) | 1987-02-09 |
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