JPS59154669U - Oscilloscope delay expansion position setting device - Google Patents

Oscilloscope delay expansion position setting device

Info

Publication number
JPS59154669U
JPS59154669U JP4845283U JP4845283U JPS59154669U JP S59154669 U JPS59154669 U JP S59154669U JP 4845283 U JP4845283 U JP 4845283U JP 4845283 U JP4845283 U JP 4845283U JP S59154669 U JPS59154669 U JP S59154669U
Authority
JP
Japan
Prior art keywords
setting device
oscilloscope
position setting
delay
expansion position
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4845283U
Other languages
Japanese (ja)
Other versions
JPS6247088Y2 (en
Inventor
勇二 濱崎
Original Assignee
株式会社島津製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社島津製作所 filed Critical 株式会社島津製作所
Priority to JP4845283U priority Critical patent/JPS59154669U/en
Publication of JPS59154669U publication Critical patent/JPS59154669U/en
Application granted granted Critical
Publication of JPS6247088Y2 publication Critical patent/JPS6247088Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Facsimiles In General (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例の構成を略示したブロック
図、第２図は第１図に示した実施例をオシロスコープに
関連して設置した状態を略示したブロック図、第３図は
その動作説明図である。　　　′１・・・・・・入力回
路、２・・・・・・記憶回路、３・・・・・・演算回路
、４・・・・・・遅延回路。Fig. 1 is a block diagram schematically showing the configuration of an embodiment of this invention, Fig. 2 is a block diagram schematically showing the embodiment shown in Fig. 1 installed in relation to an oscilloscope, and Fig. 3 is an explanatory diagram of its operation. '1...Input circuit, 2...Memory circuit, 3...Arithmetic circuit, 4...Delay circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 観測すべき走査線の線番号を入力する入力手段と、走査
周期に関連した数値を予め与えられてそれを記憶する記
憶手段と、前記入力手段から与えられる信号と前記記憶
手段に蓄えられた数値とを演算して遅延時間を算出する
演算手段と、前記演算結果に基づきメイントリがより前
記遅延時間だけ遅れた遅延トリガを出力する遅延手段と
を具備したことを特徴とするオシロスコープの遅延拡大
位置の設定装置。an input means for inputting a line number of a scanning line to be observed; a storage means for receiving and storing a numerical value related to a scanning period in advance; a signal given from the input means and a numerical value stored in the storage means; and a delay means for outputting a delay trigger in which the main trigger is delayed by the delay time based on the calculation result. Setting device.
JP4845283U 1983-03-31 1983-03-31 Oscilloscope delay expansion position setting device Granted JPS59154669U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4845283U JPS59154669U (en) 1983-03-31 1983-03-31 Oscilloscope delay expansion position setting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4845283U JPS59154669U (en) 1983-03-31 1983-03-31 Oscilloscope delay expansion position setting device

Publications (2)

Publication Number Publication Date
JPS59154669U true JPS59154669U (en) 1984-10-17
JPS6247088Y2 JPS6247088Y2 (en) 1987-12-24

Family

ID=30178982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4845283U Granted JPS59154669U (en) 1983-03-31 1983-03-31 Oscilloscope delay expansion position setting device

Country Status (1)

Country Link
JP (1) JPS59154669U (en)

Also Published As

Publication number Publication date
JPS6247088Y2 (en) 1987-12-24

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